Intel's Wireless ICs Denied Latest Processes
Intel's move on the wireless market may fail for the same reason that its X-Scale and ASIC ventures failed - because it's not putting its wireless parts on advanced processes.
It is only this year, some 18 months after Intel started running its 32nm process, that a wireless chip-set - Medfield - is going to be run on a 32nm process.
Related Semiconductor IP
- CXL 3.0 Premium Controller EP/RP/DM/SW 128-1024 bits with AMBA bridge and Advanced HPC Features (Arm CCA)
- CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge and Advanced HPC Features (Arm CCA)
- 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32b/64b RISC-V 2-stage, scalar, in-order, Embedded Processor. RTOS and multi-core capable. Maps upto ARM M-4F. Optimal PPA.
- PCIe 6.0 Controller EP/RP/DM/SW with AMBA bridge & HPC features, including Arm Confidential Compute Architecture
Related Blogs
- Intel May Exit Smartphone Market Next Year
- Why Intel will Never Succeed in IoT Market?
- Demler: Quad Core is Just For Marketing; Intel Will Not Succeed in Mobile
- ST-Ericsson: A New Force in Wireless Semiconductors (Part 1)
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?