IP Catalog > Processor IP > General Purpose Processor IP > RISC-V Processor IP > 64-Bit 8-stage superscalar RISC-V processor

64-Bit 8-stage superscalar RISC-V processor

Overview

The 64-bit NX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, and “B” bit manipulation, and Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions. It issues two instructions per cycle that significantly increases the performance efficiency that is important for many applications. Its ”B” extensions provide some combination of code size reduction, performance improvement, and energy reduction, and “FD” extensions support IEEE754-compliance single and double precision floating point instructions as well. It incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. In addition, N45 incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. Other features include ECC for memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™ and StackSafe™ for software quality improvement, PowerBrake and WFI for power management.

AndeStar™ V5 Architecture

Key Features Benefits
RISC-V RV64GCB ISA
  • State-of-the art ISA from latest developments in computer architecture
  • Industry standard and open architecture
Andes Custom Extension™ (ACE) option to create custom instructions for software acceleration
  • Add custom instruction extensions to facilitate Domain-Specific Architecture/Acceleration (DSA)
  • Boost application performance significantly, at the same time maintain the programmability
  • Powerful constructs are available to define high level instruction
  • ACE design is based on Verilog and C languages which are familiar to the designers
  • The COPILOT tool automatically generates the extended CPU and software toolchain
  • Do not require expertise in processor pipeline to design ACE instructions
Andes Extended Instructions Andes exclusive performance and functionality enhancements
16/32-bit mixable instruction format For compact code density
32 general-purpose registers For better code size and performance

CPU Core

Key Features Benefits
5.63 Coremark/MHz, 3.27 DMIPS/MHz* Excellent performance-per-MHz
8-stage dual-issue in-order pipeline Superior performance-efficiency, while allowing for high speeds

Extensive branch predication features

  • Branch Target Buffer (BTB)
  • Branch History Table (BHT)
  • Return Address Stack (RAS)
  • Branch Target Buffer and Branch History Table to speed up control codes
  • Return Address Stack to speeds up procedure returns
Physical Memory Protection (PMP), configurable up to 32 regions Basic read/write/execute memory protection with minimum cost
Programmable Physical Memory Attribute (PMA), configurable up to 16 regions

Configurable memory attributes:

  • Memory, I/O, None
  • Cacheable/Non-cacheable
  • Write-back/Write-through
  • Read/write/read & write allocate, no allocate
  • Access fault for non-existent regions
Performance monitors Program code performance tuning
StackSafe™ hardware stack protection
  • Easy identification of stack size threshold during development
  • Hardware error detection of stack overflow and underflow at runtime

Multiplier options

  • Fast multiplier: pipelined, 2-cycle
  • Small multipliers: producing 1, 2, 4, or 8 bits per cycle
 Option to choose between speed and area according to application's requirements
PowerBrake technology Performance throttling to digitally reduce power consumption
QuickNap™ technology Fast power-down/wake-up support for caches

* BSP v5.1.0, DMIPS/MHZ follows Dhrystone’s no-inline ground rules, best performances 

Memory Subsystems

Key Features Benefits

I-Cache & D-Cache

  • Size: 8KB to 64KB
  • Set associativity: Direct, 2-way or 4-way
  • Accelerating accesses to slow memories
  • Flexible cache configurations

ILM & DLM

  • Size: 4KB to 16M
  • SRAM or AXI interface support
  • Bus masters accesses by AXI slave port
  • For deterministic and efficient program execution
  • Flexible size selection to fit diversified needs
MemBoost Optimize cache reads and writes to achieve higher bandwidth and lower latency
Soft-error protection: parity for I-Cache, and ECC for D-Cache, ILM and DLM Code and data integrity protection
Bus master port: AXI with 64/128/256-bit data, I/D joint or separate bus User-selectable bus interface for optimal efficiency
Bus save port: AXI with 64/128/256-bit data, for ILM/DLM accesses Efficient data transfer between CPU and SoC masters
Core/bus clock ratio of N:1 Simplified SoC integration
64-bit AXI Peripheral Port Interface For latecny-sensitve peripheral

Platform-Level Interrupt Controller (PLIC)

Key Features Benefits

Implements RISC-V PLIC specification

  • Up to 1023 PLIC interrupt sources
  • Up to 255 PLIC interrupt priority levels
  • Up to 16 PLIC interrupt targets
 Allow individual interrupts to be serviced and prioritized without sharing

Enhanced interrupt features

  • Vectored interrupt dispatch
  • Priority-based preemption
  • Selectable edge trigger or level trigger
  • Faster interrupt handling for real-time applications
  • Complete hardware preemption support for faster response
  • Flexible interrupt source interface for simpler SoC design

Debug Support

Key Features Benefits
Implements RISC-V debug specifications ver 0.13 Supported by industry debug tool suppliers
JTAG Debug Port Industry-standard support
Embedded Debug Module with up to 8 triggers Flexible configurations to tradeoff between gate count and debugging capabilities
Exception redirection support Entering debugger upon selected exceptions without using breakpoints

Trace Support

Key Features Benefits
Implements RISC-V Trace 1.0 Instruction Trace interface Supported by Andes tools

Performance

Core, Process NX45, 7nm
Frequency (MHz) 1800
Dynamic power (uW/MHz) 14.2
Area (mm2) 0.038

TSMC 7nm FIN FET ULVT/LVT/SVT, cell height 240nm, High Speed L1 Cache Memory Compiler. Frequency condition: worst: SSGNP/0.675V/-40oc, typical: TT/0.75v/+85oc. Power and area : typical corner. Configurations: 256-entry BTB, PMP&PMA 16-entry, 32KB I/D$ (no Local Memory),  MemBoost, w/o FPU, with I/O constraint; die area and power are core only, 65% utilization.

Key Features

  • 64-bit in-order dual-issue 8-stage pipeline CPU architecture
  • AndeStar™ V5 Instruction Set Architecture (ISA)
    • Compliant to RISC-V RV64 GCBP little endian:
    • RV-GC: Integer, single/double precision floating point and 16-bit extensions
    • RV-B Bit manipulation extensions 
    • RV-P (draft) DSP/SIMD extensions
    • Andes V5 performance/code size extensions
  • 16/32-bit mixable instruction format for compacting code density
  • Advanced low power branch predication to speed up control code
  • Return Address Stack (RAS) to accelerate procedure returns
  • Physical Memory Protection(PMP), and programmable Physical Memory Attribute (PMA)
  • MemBoost for heavy memory transactions
  • Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
  • Enhancement of vectored interrupt handling for real-time performance
  • Advanced CoDense™ technology to reduce program code size

Benefits

  • Performance
    • 64-bit in-order dual-issue 8-stage pipeline CPU architecture
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • IEEE754-compliance single and double precision floating point extensions
    • Andes extensions, architected for performance and functionality enhancements
    • 16/32-bit mixable instruction format for compacting code density
    • Advanced low power branch predication to speed up control code
    • Return Address Stack (RAS) to accelerate procedure returns
    • Physical Memory Protection (PMP), and programmable Physical Memory Attribute (PMA)
    • MemBoost for heavy memory transactions
    • Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
    • Enhancement of vectored interrupt handling for real-time performance
    • Advanced CoDense™ technology to further reduce code size on top of “C” extension
  • Flexibility
    • Easy arrangement of preemptive interrupts
    • StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
    • ECC or Parity check on level-one memories for fault protection
    • Several configurations to tradeoff between core size and performance requirements
  • Power Management
    • PowerBrake, QuickNap™ and WFI (Wait For Interrupt) for power management at different occasions

Block Diagram

64-Bit 8-stage superscalar RISC-V processor Block Diagram

Applications

  • Networking and Communications
  • Video and Image Processing
  • Storage
  • Advance Industrial Controller 

Deliverables

  • AndesCore™ NX45 Single-core Processor with AE350 Platform– pre-integrated RTL with CPU subsystem (including PLIC, Debug Module) and AXI Platform

Technical Specifications

Short description
64-Bit 8-stage superscalar RISC-V processor
Vendor
Vendor Name
Request Info

Related IPs

×
Semiconductor IP