How to Model and Simulate 112Gbps PAM4 SerDes Using IBIS-AMI
With the buildout of 5G wireless networks and the constant demand for bandwidth in cloud-based data centers, serial link data rates continue to skyrocket. The current state-of-the-art serial links use 112Gbps data rates, using PAM4 signaling. PAM4 differs from traditional NRZ signaling in that it transmits 2 bits per symbol, effectively reducing the need for bandwidth by half.
To enter this hot and competitive market, Cadence purchased a startup company in late 2017 called “nusemi Inc.”, and immediately began work on a 112Gbps PAM4 SerDes IP offering.
To read the full article, click here
Related Semiconductor IP
- 1-112Gbps Serdes - 7nm
 - HDMI 2.1 TX PHY 12Gbps in TSMC N5 1.8V, North/South Poly Orientation
 - HDMI 2.1 RX PHY 12Gbps in TSMC 16FFC 1.8V, North/South Poly Orientation
 - HDMI 2.1 RX PHY 12Gbps in TSMC 12FFC 1.8V, North/South Poly Orientation
 - HDMI 2.1 Rx PHY 12Gbps in SS 14LPP, North/South Poly Orientation
 
Related Blogs
- How to Solve the Size, Weight, Power and Cooling Challenge in Radar & Radio Frequency Modulation Classification
 - How to Get Started with Model-Based Systems Engineering
 - How SerDes Became Key IP for Semiconductor Systems
 - How to Augment SoC Development to Conquer Your Design Hurdles
 
Latest Blogs
- ML-DSA explained: Quantum-Safe digital Signatures for secure embedded Systems
 - Efficiency Defines The Future Of Data Movement
 - Why Standard-Cell Architecture Matters for Adaptable ASIC Designs
 - ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware
 - Rivos Collaborates to Complete Secure Provisioning of Integrated OpenTitan Root of Trust During SoC Production