Do we need a new FPGA structure for prototyping?
Brian Bailey
EETimes (2/22/2011 1:32 PM EST)
I have been talking to a lot of people recently about the subject of prototyping. Not only do I believe that it is one of the most important applications related to the success of ESL, but to the future of design at any level of abstraction.
RTL simulation is a technology of the past, and while it still has a role to play in the verification and debug of smallish blocks, it is too slow for the kind of verification that companies are demanding before releasing a chip for production. When enough of the system is assembled to be able to see how sub-systems interact with each other, an RTL simulator is too slow or consumes too much memory to be able to simulate the types of scenarios that would allow realistic verification to be performed.
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