Do we need a new FPGA structure for prototyping?
Brian Bailey
EETimes (2/22/2011 1:32 PM EST)
I have been talking to a lot of people recently about the subject of prototyping. Not only do I believe that it is one of the most important applications related to the success of ESL, but to the future of design at any level of abstraction.
RTL simulation is a technology of the past, and while it still has a role to play in the verification and debug of smallish blocks, it is too slow for the kind of verification that companies are demanding before releasing a chip for production. When enough of the system is assembled to be able to see how sub-systems interact with each other, an RTL simulator is too slow or consumes too much memory to be able to simulate the types of scenarios that would allow realistic verification to be performed.
To read the full article, click here
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related Blogs
- Virtual Platforms plus FPGA Prototyping, the Perfect Mix
- FPGA Prototyping of System-on-Chip (SoC) Designs
- FPGA Prototyping: From Homebrew to Integrated Solutions
- Faster, Higher Capacity Emulation and Prototyping for AI Workloads
Latest Blogs
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits
- eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview