Formal verification best practices: investigating a deadlock
September 26, 2023
In our first episode from last week we focused on best practices when setting up formal verification on a component. Our setup is now ready with protocol checkers to avoid unrealistic scenarios (which also helped find a new bug), and with basic abstractions to improve performances. It’s now time to tackle our real task: reproducing a deadlock bug found using simulation. Let’s dive deep into it.
Reproducing the deadlock bug
To ensure a design is deadlock free, one approach consists in verifying that it is “always eventually” able to respond to a request. The wording is important. Regardless of the current state and the number of cycles we must wait, in the future the design must respond.
To read the full article, click here
Related Semiconductor IP
- Network-on-Chip (NoC)
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- DVB-S2 Demodulator
- UCIe PHY (Die-to-Die) IP
- UCIe-S 64GT/s PHY IP
Related Blogs
- Formal verification best practices to reach your targets
- Formal verification best practices: towards end-to-end properties
- Formal verification best practices: checking data corruption
- Formal verification best practices: sign-off and wrap-up
Latest Blogs
- Enabling End-to-End EDA Flow on Arm-Based Compute for Infrastructure Flexibility
- Real PPA improvements from analog IC migration
- Design specification: The cornerstone of an ASIC collaboration
- The importance of ADCs in low-power electrocardiography ASICs
- VESA Adaptive-Sync V2 Operation in DisplayPort VIP