Finfet's Struggles Boost Simpler, Cheaper FD-SOI
April 30, 2014
FD-SOI, seeking to grow its ecosystem, will get a boost from the remarks of KLA Tencor CEO, Rick Wallace, about the struggles his customers are having with finfets.
“In logic and foundry, with the introduction of the new 3-D gate architectures, the yield issues our customers are grappling with today are proving to be the most challenging that the industry have ever faced, and even the smallest variation and process margin can cause significant yield losses for these devices,’ says Wallace.
FD-SOI uses few masks and has less processing steps than finfet.
To read the full article, click here
Related Semiconductor IP
- ISO/IEC 7816 Verification IP
- 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
- Simulation VIP for AMBA CHI-C2C
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
Related Blogs
- FinFET vs FDSOI - Which is the Right One for Your Design?
- FD-SOI vs FinFET: Dan Hutcheson Re-Runs His Survey
- Altera vs Xilinx FinFET Update
- TSMC vs Intel vs Samsung FinFETs
Latest Blogs
- A Comparison on Different AMBA 5 CHI Verification IPs
- Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum
- Accelerating Development Cycles and Scalable, High-Performance On-Device AI with New Arm Lumex CSS Platform
- Desktop-Quality Ray-Traced Gaming and Intelligent AI Performance on Mobile with New Arm Mali G1-Ultra GPU
- Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet