FD SOI Benefits Rise at 14nm
Consultant Handel Jones makes the case that companies should move rapidly to 14nm fully depleted silicon-on-insulator (FD SOI) to use the benefits this technology.
The semiconductor and electronics industries are adapting effectively to the increase in gate costs with scaling below 28nm. The following figure shows the latest projections for gate cost.
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
Related Blogs
- FD-SOI at Samsung
- ARM 1176 in IBM SOI process demonstrates a cell-based flow
- Benefits Of Artisan Acquisition 'Coming Through', Says ARM CEO
- Jeff Bier's Impulse Response - The Rise of Licensable Cores
Latest Blogs
- Why What Where DIFI and the new version 1.3
- ML-DSA explained: Quantum-Safe digital Signatures for secure embedded Systems
- Efficiency Defines The Future Of Data Movement
- Why Standard-Cell Architecture Matters for Adaptable ASIC Designs
- ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware