Exploring AI / Machine Learning Implementations with Stratus HLS
June 20, 2019
A lot of AI design is done in software and, while much of it will remain there, increasing numbers of designs are finding their way into hardware. There are multiple reasons for this including the important goals of achieving lower power or higher performance for critical parts of the AI process. Imagine you need dramatically improved rate of object recognition in automated-driving applications.
Implementing an AI application in hardware presents some key challenges for the designer.
- Need to explore multiple algorithms and architectures, typically using a framework such as TensorFlow or Caffe
- Need to qualify power, performance, area, and accuracy trade-offs of various architectures
- Need a rapid path from the models to production silicon
In this article, I'll describe a flow that starts in the TensorFlow environment, moves into abstract C++ targeted at the Stratus HLS flow, and then into a concrete hardware implementation flow.
To read the full article, click here
Related Semiconductor IP
- 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
- Simulation VIP for AMBA CHI-C2C
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
Related Blogs
- Take your neural networks to the next level with Arm's Machine Learning Inference Advisor
- Enabling ‘Few-Shot Learning’ AI with ReRAM
- Designing the AI Factories: Unlocking Innovation with Intelligent IP
- Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach
Latest Blogs
- Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet
- Arm and Synopsys: Delivering an Integrated, Nine-Stage “Silicon-to-System” Chip Design Flow
- Accelerate Automotive System Design with Cadence AI-Driven DSPs
- What Makes FPGA Architecture Ideal for Ultra-Low-Latency Systems?
- Introducing agileSecure anti-tamper security portfolio