Exploring AI / Machine Learning Implementations with Stratus HLS
June 20, 2019
A lot of AI design is done in software and, while much of it will remain there, increasing numbers of designs are finding their way into hardware. There are multiple reasons for this including the important goals of achieving lower power or higher performance for critical parts of the AI process. Imagine you need dramatically improved rate of object recognition in automated-driving applications.
Implementing an AI application in hardware presents some key challenges for the designer.
- Need to explore multiple algorithms and architectures, typically using a framework such as TensorFlow or Caffe
- Need to qualify power, performance, area, and accuracy trade-offs of various architectures
- Need a rapid path from the models to production silicon
In this article, I'll describe a flow that starts in the TensorFlow environment, moves into abstract C++ targeted at the Stratus HLS flow, and then into a concrete hardware implementation flow.
To read the full article, click here
Related Semiconductor IP
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
- Neuromorphic Processor IP
Related Blogs
- Enabling ‘Few-Shot Learning’ AI with ReRAM
- Alif Is Creating SoC Solutions for Machine Learning with Cadence and Arm
- Take your neural networks to the next level with Arm's Machine Learning Inference Advisor
- From All-in-One IP to Cervell™: How Semidynamics Reimagined AI Compute with RISC-V
Latest Blogs
- Analog Design and Layout Migration automation in the AI era
- UWB, Digital Keys, and the Quest for Greater Range
- Building Smarter, Faster: How Arm Compute Subsystems Accelerate the Future of Chip Design
- MIPS P8700 RISC-V Processor for Advanced Functional Safety Systems
- Boost SoC Flexibility: 4 Design Tips for Memory Subsystems with Combo DDR3/4 Interfaces