Codasip's Expanding RISC-V Offering
In the last three months, Codasip’s RISC-V processor offering has expanded considerably. For some years, Codasip has supplied Bk3 and Bk5 RISC-V cores aimed at low- to medium-complexity embedded applications. But recently four additional cores have joined the Codasip RISC-V offering.
Three of the cores, the SweRV Core™ EH1, EH2 and EL2, were designed by Western Digital and were open-sourced through CHIPS Alliance. These 32-bit cores are mainly aimed at high-performance embedded applications and complement the existing 32-bit Bk3 and Bk-5 cores. The EH1 offers outstanding embedded performance due to its superscalar, dual issue architecture. Even more performance is delivered by the EH2 which provides two hardware threads (harts). The EL2 core is more compact and is a single-issue core.
To read the full article, click here
Related Semiconductor IP
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
- All-In-One RISC-V NPU
Related Blogs
- The Challenges of Making Open-Source RISC-V Deployment Effective
- Open Source vs Commercial RISC-V Licensing Models
- Customizing an Existing RISC-V Processor
- Is RISC-V the Future?
Latest Blogs
- From guesswork to guidance: Mastering processor co-design with Codasip Exploration Framework
- Enabling AI Innovation at The Far Edge
- Unleashing Leading On-Device AI Performance and Efficiency with New Arm C1 CPU Cluster
- The Perfect Solution for Local AI
- UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics