Arteris vs Sonics battle...Let's talk NoC architecture
November 4, 2011
The Network on Chip is a pretty recent concept. Let’s try to understand how it works. Anybody who has been involved in the Supercomputer design (like I was in the 80’s), knows that you need a “piece” between the multiple CPU and memory banks, at that time a “crossbar switch”. To make it outrageously simple, you want to interconnect the M blocks on the left side with the N blocks on the right side, to do so you create a switch made of MxN wires.
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
Related Blogs
- Breaking Down the "Make vs. Buy" Barriers for IP
- 2024 Set The Stage For NoC Interconnect Innovations In SoC Design
- From DIY To Advanced NoC Solutions: The Future Of MCU Design
- NoC 102: Using SonicsGN to Address Low Power Requirements From IoT to Servers
Latest Blogs
- Why What Where DIFI and the new version 1.3
- Accelerating PCIe Gen6 L0p Verification for AI & HPC Designs using Synopsys VIP
- ML-DSA explained: Quantum-Safe digital Signatures for secure embedded Systems
- Efficiency Defines The Future Of Data Movement
- Why Standard-Cell Architecture Matters for Adaptable ASIC Designs