ARM Cortex-A9 SMP Design Announced
September 17, 2009
ARM just announced a couple of 2-core SMP design based upon the Cortex-A9 application processor, one optimized for performance and the other for power consumption. Although the optimization points are different, both are incredibly low power consumers by server standards with the performance-optimized part dissipating only 1.9W at 2Ghz based upon the TSMC 40G process (40nm). This design is aimed at server applications and should be able to run many server workloads comfortably.
To read the full article, click here
Related Semiconductor IP
- SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP
- OpenTitan-based RISC-V Secure Element
- TSMC 40nm 5V GPIO
- Low Power 32kHz Pierce Oscillator
- Time-Sensitive Networking (TSN) End Point DO-254 IP Core
Related Blogs
- Processor Wars: NVIDIA reveals a phantom fifth ARM Cortex-A9 processor core in Kal-El mobile processor IC. Guess why it's there?
- Cortex-M55: Functional Safety ready and fuelling the next generation of automotive microcontrollers
- Arm Safety Ready program: Building confidence into your application
- Wind River and Arm collaboration accelerates journey to functional safety compliance in centralized vehicle controllers
Latest Blogs
- Rethinking RTL flows with AI-driven hybrid formal verification
- Arm and NVIDIA: Building the trusted compute foundation for the agentic AI era
- Trusted Autonomy with Cadence Super Agents & NVIDIA Open Agent Safety Platform
- One Processor, One Toolchain
- Akida Execution in Heterogeneous Environments - Clone It, Build It, Run It