Are We There Yet? Metric-Driven Signoff
October 16, 2017
Are we there yet? All verification suffers from the problem of trying to decide when enough verification has been done. It is not possible to exhaustively simulate everything on a chip and so completeness cannot be the criterion (exhaustion, however, is optional, usually on the part of the design team).
At CDNLive in Bengaluru, Narender Kumar and Ravin Shah of ST Microelectronics (and Anshul Singhal of Cadence) presented on vManager Metric-Driven Signoff Platform for SoC Verification.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Complex Digital Up Converter
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
Related Blogs
- Verification Panel: Are We Done Yet? Not Even Close
- Are we on the verge of a new ASIC era? DARPA’s Nanowriter and practical e-beam lithography
- Are there any FPGA tool developers out there?
- Are we about to reach end of Moore’s Law?
Latest Blogs
- CNNs and Transformers: Decoding the Titans of AI
- How is RISC-V’s open and customizable design changing embedded systems?
- Imagination GPUs now support Vulkan 1.4 and Android 16
- From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success
- Accelerating RTL Design with Agentic AI: A Multi-Agent LLM-Driven Approach