Are Standard Cell Libs, Memories and Mixed-signal IP Available at 7nm FF?
More than 500 designers (562) have responded to a survey made in 2015 by Synopsys. Answering to the question “What is the fastest clock speed of your design?” 56% have mentioned a clock higher than 500 MHz (and still 40% higher than 1 GHz). If you compare with the results obtained 10 years ago, the largest proportion of answers was for clock ranging between 100 MHz to 300 MHz.
That means that Moore’s law has been extremely effective during the last ten years, and also that for a high proportion of designs, speed improvement is a real need. These designs are the natural candidates to target FinFET technologies. From the graph below, you see that moving from 28nm (bulk) to 14nm FF can provide 45% faster frequency, at constant dynamic & leakage power, each step below, 10nm and 7nm, providing another 20% improvement.
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
Related Blogs
- How Synopsys IP and TSMC's N12e Process are Driving AIoT
- 70% of re-spin issues are AMS in nature: How mixed-signal design can mess up a perfectly good SoC
- Qualcomm: Scaling down is not cost-economic anymore - so we are looking at true monolithic 3D
- Who Needs to Lead at the 14, 10 and 7nm nodes
Latest Blogs
- Why What Where DIFI and the new version 1.3
- ML-DSA explained: Quantum-Safe digital Signatures for secure embedded Systems
- Efficiency Defines The Future Of Data Movement
- Why Standard-Cell Architecture Matters for Adaptable ASIC Designs
- ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware