3D and power is all wet
There has been a lot of talk recently about 3D ICs and the challenges associated with them. One area that contains some of the biggest challenges is related to power – how do you get power in and how do you get the heat generated back out again. To understand this a little more, I talked to Madhavan Swaminathan who is the Joseph M. Pettit Professor in Electronics at the School of Electrical and Computer Engineering and Director of the Interconnect and Packaging Center (IPC), an SRC Center of Excellence, at Georgia Tech, Atlanta. He is also the Founder and CTO of E-System Design.
I featured the introductory chapter of his book “Power Integrity Modeling and Design for Semiconductors and Systems” during my EDA Designline series about power in April. This book chapter provides a good background into the power delivery network and its analysis.
To read the full article, click here
Related Semiconductor IP
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
Related Blogs
- Do Foundries Have Too Much Power?
- Bringing Power Efficiency to TinyML, ML-DSP and Deep Learning Workloads
- What Is the OSI Model, and How Can We Protect Its Critical Layers?
- The Future of PCIe Is Optical: Synopsys and OpenLight Present First PCIe 7.0 Data-Rate-Over-Optics Demo
Latest Blogs
- How Arasan’s SoundWire PHY Can Elevate Your Next Audio SoC
- Cadence Leads the Way at PCI-SIG DevCon 2025 with Groundbreaking PCIe 7.0 Demos
- Introducing the Akeana 1000 Series Processors
- How fast a GPU do you need for your user interface?
- PCIe 6.x and 112 Gbps Ethernet: Synopsys and TeraSignal Achieve Optical Interconnect Breakthroughs