中国RSIC-V热潮持续升温
Andes, Gowin gear up cores, FPGAs
By Rick Merritt, EETimes (November 15, 2018)
SANTA CLARA, Calif. — Momentum is growing in China for RISC-V, according to reports from two vendors at an event here. Andes detailed six cores it currently sells and four more in the works using the open-source instruction set architecture, and GoWin demonstrated FPGAs using them.
Overall, RISC-V shipments are still tiny compared to those of rivals such as Arm, but growth of its adoption and ecosystem “is moving in the right direction,” said one market watcher.
“In China, pretty much every company is asking for RISC-V, and they think it should include everything” Arm cores have, said Charlie Su, chief technology officer for Andes, a Taiwan-based core vendor that does 30% of its business in the People’s Republic.
So far, Andes has 12 licensees worldwide for its RISC-V cores. Their uses range from storage servers and fingerprint recognizers to several AI apps, he said.
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Related Semiconductor IP
- RISC-V CPU IP
- RISC-V Vector Extension
- RISC-V Real-time Processor
- RISC-V High Performance Processor
- 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
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