IP Catalog > Processor IP > General Purpose Processor IP > RISC-V Processor IP > ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core

ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core

Overview

The D23-SE is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications with small gate count, and some dual-issue ability. In addition to commonly used RISC-V IMAC, single/double precision FPU and DSP extensions, it supports the recently ratified ISA extensions such as B (bit manipulation), K (scalar cryptography), CMO (cache management operations) as well as Zce (code size reduction), plus Andes Custom Extension™ (ACE) for user-defined instructions. D23-SE supports split-mode that 2 cores could run independently when split-lock is configured. Safety features include dual-core lockstep (DCLS) that is a real-time diagnostic using an additional processor and a comparator to enhance the diagnostic coverage; ECC for memory soft error protection; bus protection to protect bus transaction; core trap status bus interface provides real time information of trap status from core. Approved based on the functional safety assignments of a Safety Element Out-of-Context (SEooC), which includes the ISO 26262 compliant development process and the qualitative as well as quantitative approaches with respect to hardware safety analysis, D23-SE is certified to be ASIL-B/D and used in highest safety-related applications.

Key Features and Performance

AndeStar™ V5 (RV32I) 32-bit Architecture

Key Features Benefits
  • RISC-V RV32 I, M, A, B, C, P* instructions
  • F, D, K, CMO, Zce instructions planned in revision update
  • State-of-the art ISA from latest developments in computer architecture
  • Industry standard and open architecture
Andes Extended Instructions Andes exclusive performance and functionality enhancements
16/32-bit mixable instruction format For compact code density
32 general-purpose registers For better code size or performance
  • Machine (M), optional User (U) Privilege levels
  • Optional Supervisor (S) Privilege level planned in revision update
 Embedded systems with privilege protections

*P-extension is in draft

CPU Core

Key Features Benefits
2.0 DMIPS/MHz, 4.5 CoreMark/MHz Superior performance-per-MHz
3-stage pipeline Optimized for gate count and efficiency
Static or dynamic branch predication Speed up branch control codes
  • Enhanced Physical Memory Protection (ePMP), up to 32 entries
  • Supervisor mode PMP (sPMP), up to 32 entries, planned in revision update
 Enhance core security
Programmable Physical Memory Attributes (PPMA), up to 8 regions Basic read/write/execute memory protection with minimum cost
Performance monitors Performance tuning
StackSafe™ hardware stack protection, planned in revision update
  • Easy identification of stack size threshold during development
  • Hardware error detection of stack overflow and underflow at runtime

Multiplier options:

  • Pipelined with 2-cycle latency, or
  • Sequential with 1/2/4/8-bit results per cycle
 Option to choose between speed and area according to application's requirements

Power Management

  • PowerBrake technology, planned in revision update
  • WFI(Wait for Interrupt) and WFE(Wait for Event)
 Performance throttling to digitally reduce power consumption WFI instruction and WFE CSR for software power control

Memory Subsystems

Key Features Benefits

Unified read-only instruction cache, or Instruction and Data Caches

  • Configurable from 1KB up to 32KB
  • Parity for I$; ECC for I$/D$
  • Accelerating accesses to slow memories
  • Flexible cache configurations

I/D Local Memory

  • Size: Individually configurable from 1KB up to 512MB with ECC protection
  • SRAM or AHB-Lite interface support
  • For deterministic and efficient program execution
  • Flexible size selection to fit diversified needs

Bus interfaces

Key Features Benefits
  • 32-bit AHB-L System Port - synchronous N:1 core-to-bus clock ratio
  • 32-bit AHB-L Low Latency Port
  • 32-bit APB Peripheral Port
  • 32-bit AHB-L Local Memory Access Port
  • System Port with synchronous N:1 core-to-bus clock ratio to provide user-selectable bus interface for optimal efficiency and ease SoC integration
  • Low Latency Port for latency-sensitive peripherals
  • APB interface for private peripherals
  • Local Memory Access Port allows external bus master to access local memory

Core-Local Interrupt Controller (CLIC)

Key Features Benefits
Up to 1002 interrupt sources, and up to 255 interrupt priority levels Allow core local interrupts to be serviced and prioritized without sharing

Enhanced interrupt features

  • Selective vectoring with priority preemption
  • Support for software-based tail chaining
  • Faster interrupt handling for real-time applications
  • Complete hardware preemption support for faster response
  • Flexible interrupt source interface for simpler SoC design

Platform-Level Interrupt Controller (PLIC)

Key Features Benefits

Implements RISC-V PLIC specification

  • Up to 1023 interrupt sources
  • Up to 255 interrupt priority levels
 Interrupt handling for SoC with multiple processors

Enhanced interrupt features

  • Priority-based preemption
  • Selectable edge trigger or level trigger
 Complete hardware preemption support

Debug Support

Key Features Benefits
Implements RISC-V debug specifications Supported by industry debug tool suppliers
2-wire serial or 4-wire JTAG Industry-standard support
Embedded Debug Module with 2/4/8 triggers Flexible configurations to tradeoff between gate count and debugging capabilities
Optional password-based secure debug Enhanced secure debugging

Trace Support

Key Features Benefits
RISC-V Processor Trace v2.0 support Support instruction trace according to RISC-V standard

Key Features

  • AndeStar™ V5 ISA, including:
    • RV32 I,M,A,C,F,D,B,P,K,CMO, and Zce
    • Andes extensions for performance and functionality enhancements
  • 3-stage pipeline optimized for gate count and efficiency
  • 16/32-bit mixable instructions for code density
  • Instruction and data caches to speed up accessing embedded or external flash memory
  • Branch predication to speed up control code
  • Enhanced and Supervisor-mode Physical Memory Protection (ePMP and sPMP) to enhance core security
  • Core-Local Interrupt Controller (CLIC) for fast response, interrupt prioritization and pre-emption and Platform-Level Interrupt Controller (PLIC) for a wide range of cores and system event scenarios
  • Patented CoDense™ technology to compress program code on top of the 16-bit extension
  • Instruction Trace Interface supports RISC-V Processor Trace v2.0
  • Fast interrupt response with shadow registers
  • Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
  • Functional Safety
    • AndesCore™ D23-SE processor core certified by parts 2, 4, 5, 7, 8 and 9 of the standards, meeting the architectural metrics and random hardware fault metrics requirements for ASIL B/D 
    • D23-SE supports split-mode that 2 cores could run independently when split-lock is configured. ECC for memory soft error protection; bus protection to protect bus transaction; core trap status bus interface provides real time information of trap status from core.
    • Safety Mechanism: Split/Lock (ASIL-B/D); Single Core (ASIL-B)
  • Development Tools
    • AndeSight™ Integrated Development Environment (Eclipse-based)
    • ICE debugging hardware
    • Three product name: D23-SE-DCLS; D23-SE-DCLS-LOCK; D23-SE-SC

Block Diagram

ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core Block Diagram

Technical Specifications

Request Info

Related IPs

×
Semiconductor IP