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ML-DSA

ML-DSA (FIPS 204, formerly CRYSTALS-Dilithium): This algorithm is also based on lattice problems but is specifically designed for digital signatures, offering strong security guarantees and efficient performance.

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Compare 17 ML-DSA from 8 vendors (1 - 10)
  • CRYSTALS Dilithium core for accelerating NIST FIPS 204 Module Lattice Digital Signature algorithm
    • Hardware core for accelerating the high-level operations specified in the NIST FIPS 204 standard.
    Block Diagram -- CRYSTALS Dilithium core for accelerating NIST FIPS 204 Module Lattice Digital Signature algorithm
  • APB Post-Quantum Cryptography Accelerator IP Core
    • Implements ML-KEM and ML-DSA post-quantum cryptography digital signature standards. The system interface is an microprocessor slave bus (APB, AHB, AXI options are available).
    • The design is fully synchronous and requires only minimal CPU intervention due to internal microprogramming sequencer.
    Block Diagram -- APB Post-Quantum Cryptography Accelerator IP Core
  • Falcon IP Core
    • Falcon IP Core is a post-quantum digital signature algorithm (DSA).
    • It is currently under development. It is going to be compliant with Falcon specification submitted on round 3 of NIST Post-Quantum Cryptography Standardization process.
    • Additionally, Falcon IP Core will be enhanced to achieve compliance with NIST Falcon Standart when it is released. 
    Block Diagram -- Falcon IP Core
  • Dilithium IP Core
    • Dilithium IP Core is a post-quantum digital signature algorithm (DSA).
    • It currently supports Sign and Verify functions, with key generation functionality planned for future implementation.
    • This IP is compliant with Dilithium specification submitted on round 3 of NIST Post-Quantum Cryptography Standardization process.
    Block Diagram -- Dilithium IP Core
  • Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
    • PQCryptoLib-Emebedded is a versatile, CAVP-ready cryptography library designed and optimized for embedded devices.
    • With its design focused on ultra-small memory footprint, PQCryptoLib-Embedded solutions have been specically designed for embedded systems, microcontrollers and memory-constrained devices. It provides a PQC integration to devices already in the field.
    Block Diagram -- Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
  • Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
    • The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
    • Symmetric operations are offloaded very efficiently as it has a built-in scatter/gather DMA. The coprocessors can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
    Block Diagram -- Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
  • Post-Quantum Cryptography Processor
    • PQPlatform-CoPro (PQP-HW-COP) adds PQShield’s state-of-the-art post-quantum cryptography (PQC) to your security sub-system, with optional side-channel countermeasures (SCA).
    • PQPlatform-CoPro can be optimized for minimum area as part of an existing security sub-system.
    • PQPlatform-CoPro is designed to be run by an existing CPU in your security system, using PQShield’s supplied firmware.
    Block Diagram -- Post-Quantum Cryptography Processor
  • Lattice-based Post-Quantum Cryptography Processing Engine
    • PQC(post-quantumcryptography) engine
    • NISTSP800-56Acomplaint
    • NISTFIPS186-4and186-5compliant
    • ANSSIX9.142-2020compliant
    Block Diagram -- Lattice-based Post-Quantum Cryptography Processing Engine
  • Self-contained cryptographic subsystem designed for PQC + classical, minimal integration effort, with SCA protection
    • A cryptographic subsystem, designed to provide cryptographic services.
    • These services include post-quantum signature generation, verification, and secure key establishment.
    • PQPlatform-SubSys uses its built-in CPU independently from the surrounding system, allowing cryptographic services to be offloaded efficiently from the system processor.
    Block Diagram -- Self-contained cryptographic subsystem designed for PQC + classical, minimal integration effort, with SCA protection
  • High-speed, high-throughput, lattice PQC cryptographic subsystem
    • A powerful hardware-based product that is designed for high throughput and high speed.
    • PQPerform-Lattice adds post-quantum cryptography for applications that handle a large number of transactions, such as high-capacity network hardware applications or HSMs (hardware security modules) requiring fast performance.
    • It’s designed for performance and supports FIPS 204 ML-DSA digital signatures for quantum-secure authentication and FIPS 203 ML-KEM for quantum-secure key exchange.
    Block Diagram -- High-speed, high-throughput, lattice PQC cryptographic subsystem
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