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Search (21)
Compare 21 ECC from 10 vendors (1 - 10)
  • PKC Multi Hardware Accelerator IP
    • The PKC Multi hardware accelerator is a secure connection engine that can be used to offload the compute intensive Public Key operations (Diffie-Hellman Key Exchange, Signature Generation and Verification), widely used for High-performance TLS Handshake.
    Block Diagram -- PKC Multi Hardware Accelerator IP
  • Public Key Crypto Engine
    • The Public Key Crypto Engine is a versatile IP core for hardware offloading of all asymmetric cryptographic operations.
    • It enables any SoC, ASIC and FPGA to support efficient execution of RSA, ECC-based algorithms and more.
    • The IP core is ready for all ASIC and FPGA technologies.
    Block Diagram -- Public Key Crypto Engine
  • Scalable RSA and Elliptic Curve Accelerator
    • The core implements the exponentiation operation of the RSA cryptography Q = Pk.
    • The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started.
    • Once the operation is complete, the result Q can be read through the interface.
    Block Diagram -- Scalable RSA and Elliptic Curve Accelerator
  • NIST P-256/P-384 ECDH+ECDSA - Compact ECC IP Cores supporting ECDH and ECDSA on NIST P-256/P-384
    • Minimal Resource Requirements
    • Secure Architecture
    • FIPS 186-4 and SP 800-56A compliant
    Block Diagram -- NIST P-256/P-384 ECDH+ECDSA - Compact ECC IP Cores supporting ECDH and ECDSA on NIST P-256/P-384
  • ECDSA IP Core
    • ECDSA IP Cores perform digital signature generation and verification in compliance with the Elliptic Curve Digital Signature Algorithm (ECDSA) specifications defined in 'FIPS 186'.
    • This standard specifies methods for digital signature generation and verification using the Elliptic Curve Digital Signature Algorithm (ECDSA). 
    Block Diagram -- ECDSA IP Core
  • High-Speed Elliptic Curve Cryptography Accelerator for ECDH and ECDSA
    • Fully digital design
    • Portable to any ASIC or FPGA technology
    • Fully standard compliant
    • Easy to integrate
    Block Diagram -- High-Speed Elliptic Curve Cryptography Accelerator for ECDH and ECDSA
  • RSA/ECC Public Key Accelerators with TRNG and AHB
    • Up to 4160-bit modulus size for RSA & 768-bit modulus for prime field ECC operations
    • Public key signature generation, verification and key negotiation with little involvement of host
    • NIST CAVP compliant for FIPS 140-3
    Block Diagram -- RSA/ECC Public Key Accelerators with TRNG and AHB
  • Small RSA/ECC Public Key Accelerators
    • The PKA-IP-28 is a family of Public Key Accelerator IP cores designed for full scalability and an optimal “performance over gate count” deployment.
    • Proven in silicon, the PKA-IP-28 public key accelerator addresses the unique needs of semiconductor OEMs and provides a reliable and cost-effective solution that is easy to integrate into SoC designs.
    Block Diagram -- Small RSA/ECC Public Key Accelerators
  • Block Diagram -- 100% Secure Cryptographic System for RSA, Diffie-Hellman and ECC with AMBA AHB, AXI4 and APB
  • Asymmetric cryptographic accelerator
    • The ACrypto Engine is an asymmetric cryptographic accelerator suitable for embedded application.
    • It provides capability for basic arithmetic and frequently used operations. Along with driver, it is flexible to support popular upperlayer applications.
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