IP Catalog > Security IP > Cryptography IP > Hash and HMAC Accelerator IP > MD5 Processor

MD5 Processor

Overview

This core is a fully compliant implementation of the Message Digest Algorithm MD5. It computes a 128-bit message digest for messages of up to (264 – 1) bits. Simple, fully synchronous design with low gate count.

The OL_MD5 core is a fully compliant hardware implementation of the MD5 algorithm, suitable for a variety of applications. 

The MD5 algorithm is an improved version of MD4, created by Professor Ronald L. Rivest of MIT  and is closely modelled after that algorithm. It operates on message blocks of 512 bits for which  a 128-bit (4 x 32-bit words) digest is produced. Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the message of the whole message.

Key Features

  • RFC 1321 compliant.
  • Suitable for data authentication applications.
  • Fully synchronous design.
  • Available as fully functional and synthesizable VHDL or Verilog soft-core.
  • FPGA netlist available for various devices.

Block Diagram

MD5 Processor Block Diagram

Applications

  • Electronic Funds Transfer.
  • Authenticated Electronic data transfer.
  • Encrypted data storage.

Deliverables

  • Available as fully functional and synthesizable VHDL or Verilog soft-core.
  • Xilinx and Altera netlist available for various devices.

Technical Specifications

Short description
MD5 Processor
Vendor
Vendor Name
Foundry, Node
Xilinx and Altera netlist available for various devices
Availability
now
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