Secure Hash Algorithm 256 IP Core
Overview
A universal solution that effectively accelerates the SHA2-256 hash function conforming with FIPS PUB 180-4 is the SHA2-256 bridge to APB, AHB, and AXI bus. It has two modes for computing message digests: 256-bit and 224-bit. A message length of up to 264 +/- 1 bit may be entered. It also natively supports the SHA2-256 HMAC (Keyed-Hash Message Authentication Code), a cryptographic function defined in RFC 2104. This depends on the core settings. This IP is appropriate for secure communication in general as well as for verifying data integrity and authenticity in digital signature methods. It may also be applied to speed up calculations related to cryptocurrencies.
Key Features
- FIPS PUB 180-4 compliant SHA2-256 function
- RFC 2104 compliant HMAC mode native support
- SHA2 224 and 256 bit modes support
- Secure storage for precomputed HMAC keys
- Hash/HMAC context swapping
- Internal, automatic padding module
- Binary message resolution support
- Flexible data read/write modes
- Software driver with OpenSSL/MbedTLS interface ready
- Available system interface wrappers:
- AMBA – APB / AHB / AXI Bus
- Altera Avalon Bus
- Xilinx OPB Bus
Block Diagram
Applications
- Digital signature
- Data integrity
- Key derivation
- TLS/SSH/PGP IPsec communication
Deliverables
- Source code:
- VERILOG test bench environment
- Technical documentation
- Synthesis scripts
- Example application
- Technical support
Technical Specifications
Maturity
In Production
Availability
Immediately