This core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (264 – 1) bits. Simple, fully synchronous design with low gate count.
SHA-256 Processor
Overview
Benefits
- FIPS 180-2 compliant.
- Suitable for data authentication applications.
- Fully synchronous design.
- Available as fully functional and synthesizable VHDL or Verilog soft-core.
- FPGA netlist available for various devices.
Technical Specifications
Availability
Now