SHA-1 Processor

Overview

This core is a fully compliant implementation of the Secure Hash Algorithm, SHA-1. It computes a 160-bit message digest for messages of up to (2⁶⁴ – 1) bits. Simple, fully synchronous design with low gate count.

The OL_SHA core is a fully compliant hardware implementation of the SHA-1 algorithm, suitable for a variety of applications.

The SHA-1 algorithm is based on principles similar to those used by Professor Ronald L. Rivest of MIT when designing the MD4 message digest algorithm, and is closely modeled after that algorithm. It operates on message blocks of 512 bits for which a 160-bit (5 x 32-bit words) digest is produced. Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the digest of the whole message.

Key Features

Suitable for data authentication applications.
Fully synchronous design.
Available as fully functional and synthesizable VHDL or Verilog soft-core.
Xilinx and Altera netlist available for various devices.

Block Diagram

Applications

Electronic Funds Transfer.
Authenticated Electronic data transfer.
Encrypted data storage.

Deliverables

Available as fully functional and synthesizable VHDL or Verilog soft-core.
Xilinx and Altera netlist available for various devices.

Technical Specifications

Availability

now

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