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Compare 631 IP from 18 vendors (1 - 10)
  • Standard Cell Library in SkyWater 90nm
    • This Standard Cell Library is a production-ready, low-leakage digital logic library developed for the SkyWater 90nm (S90 / C9) process.
    • Built on a proven standard cell architecture, the library provides comprehensive combinational, sequential, clocking, and power-management cells optimized for reduced standby power, predictable PPA, and robust SoC integration.
  • Standard Cell Library
    • Basic Cells: A full suite of fundamental logic gates and flip-flops.
    • Optimal Cells: High-performance variants of basic cells, optimized for power, area, and speed, including high-speed flip-flops, advanced multiplexers, clock gated cells, clock buffers, arithmetic cells and custom-designed cells for critical paths.
  • Standard Cell Library, Low Voltage Operation 0.45 V TSMC N3P
    • Nominal voltage of 0.75 V +/-10 %
    • Low voltage of 0.45 V +/-10 %
    • Track height: 7.5T
    • Operating temperature: -40°C to 125°C
  • Digital Standard Cell Library
    • The agileDSCL is a compact Digital Standard Cell Library customizable for specific foundries and processes, and optimized for low-power, ultra-low-leakage, high-density or high-speed applications.
    • It provides a selection of standard cells with functionalities essential to implement digital designs, with an additional power management library to support the implementation of low-power designs.
  • SMIC 0.13um 6 track High Density Standard Cell Library - HVT,1.2v operating voltage
    • SMIC 0.13um Logic 1P8M 1.2V/3.3V process
    • Wide Variety of Cell Functions and Drive Strengths
    • Process-Specific Optimization for High-Density, High-Speed, and Low-Power
    • Engineered for Synthesizability and Routability
  • 6 track High Density standard cell library at TSMC 180nm
    • High Density optimization
  • 9 track Near Threshold Voltage standard cell library at TSMC 55 nm
    • Extended Battery Life
    • Enable Always-on block to operate up to several MHz
    • Ultra Low Voltage Capability for additional power savings when operating down to 0.75V +/- 10%
    • Simplification of Power Management Network
  • 6 track Ultra High Density standard cell library at TSMC 180 nm
    • Ultra High-Density
    • Up to 19% denser after P&R compared to existing 7-Track library
    • 6-Tracks logic library for optimal area reduction
    • Pulsed latches as Spinner Cells instead of flip-flops: for up to 30% gain in density at cell level
  • Standard Cell Library in TSMC (12nm~180nm)
    • -Ultra-High-Density Standard Cell Library (HDSC) for highest density, lowest cost and lowest power
    • -General Purpose Standard Cell Library (GPSC) for general purpose logic with balanced PPA
    • -Ultra-High Speed Standard Cell Library (HSSC) for the optimized performance in the critical path
    • -Low Leakage Standard Cell library (LLSC) for ultra-low-leakage
  • SEC 10nm Multi-Bit Standard Cell Library, 0.45V operation voltage
    • SEC 10nm LPP process
    • Special Cell Library for Multi-Bit Flip-Flop application
    • Ultra Low Voltage
    • Compatible with SEC's general Standard Cell Library
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Semiconductor IP