Silvaco’s low voltage Standard Cell Library for the TSMC N3P process represents a breakthrough in power efficiency for high performance SoC designs. A nominal operating voltage of 0.75 V coupled with a low voltage
operation of 0.45 V, Silvaco’s N3P Standard Cell Libraries enable designers the greatest flexibility in managing the power efficiency for any design.
Standard Cell Library, Low Voltaage TSMC N3P
Overview
Key Features
- Nominal voltage of 0.75 V +/-10 %
- Low voltage of 0.45 V +/-10 %
- Track height: 7.5T
- Operating temperature: -40°C to 125°C
- Extensive cell set with fine grained drive strengths
- Optimized for performance and yield with Silvaco tools
- Library augmented with over 150 cells optimized for
- performance at 0.45 V
Deliverables
- Views
- Verilog gate-level
- Liberty Files (timing and power)
- GDSII
- LVS Netlist
- Datasheet
Technical Specifications
Foundry, Node
TSMC, 3nm
Maturity
Pre-silicon
Availability
Now
Related IPs
- Standard Cell Library in TSMC (12nm~180nm)
- 6 track High Density standard cell library at TSMC 180nm
- UCIe-S PHY for Standard Package (x32) in TSMC N3P, East/West Orientation
- UCIe-S PHY for Standard Package (x32) in TSMC N3P, North/South Orientation
- SMIC 0.13um General Process, 1.2V/2.5V Standard Cell Library
- SMIC 0.13um High Vt Process, 1.2V/2.5V standard cell Library