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eDP IP

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Search (47)
Compare 47 IP from 15 vendors (1 - 10)
  • eDP TRANSMITTER IIP
    • Supports eDP 1.4b specification
    • Supports full eDP Transmitter functionality
    • Supports multi lanes upto 4 lanes.
    • Supports main link, Aux link and Hot plug functionality.
    Block Diagram -- eDP TRANSMITTER IIP
  • eDP RECEIVER IIP
    • Supports eDP 1.4b specification
    • Supports full eDP Receiver functionality
    • Supports multi lanes upto 4 lanes.
    • Supports main link, Aux link and Hot plug functionality.
    Block Diagram -- eDP RECEIVER IIP
  • eDP 1.5 Verification IP
    • Fully compliant with VESA Embedded DisplayPort (eDP) Standard 1.5 Specification
    • Supports power saving feature:- Panel Self Refresh features PSR/PSR2, PR, Adaptive sync, and backlight control.
    • Supports HDCP version 1.4, 2.2 and 2.3
    • Supports Alternative Scrambler Seed Reset (ASSR)
      • TPS4 with ASSR is supported
    Block Diagram -- eDP 1.5 Verification IP
  • eDP PHY
    • Compatible with embedded display port v1.5/v1.4b specification 
    • Four-lane main link with support for 8.1/5.4/4.32/3.24/2.7/2.43/2.16/1.62Gbps 
    • Supports Enhanced Framing Mode 
    • Automatic Link-Training with an option for firmware-controlled Link-Training procedure 
    Block Diagram -- eDP PHY
  • eDP 1.3 Transmitter PHY
    • Fully compliant to VESA Embedded DisplayPort 1.3 specifications
    • Support Embedded DisplayPort RBR, HBR, and HBR2 data rate and customized data rate
    • Configurable x1/x2/x4 Main-Link data lanes
    • PIPE SerDes Mode interface to Embedded DisplayPort controller
  • eDP 1.5a RX PHY Samsung 14nm
    • Compliant to DisplayPort v1.4, eDP v1.4, and eDP v1.5a
    • Supports data rates from Reduced Bit Rate (RBR:1.62 Gbps) to High Bit Rate 3 (HBR3: 8.1Gbps), and user configurable custom B/Ws
    • Supports for eDP v1.4b features, such as PSR1 and PSR2
    Block Diagram -- eDP 1.5a RX PHY Samsung 14nm
  • eDP 1.4 Receiver
    • Compliant with Embedded DisplayPort 1.4 specification
    • Support for up to 4 Dual-Speed lanes at 1.62 Gbit/s and 2.7 Gbit/s
    • Supports Enhanced Framing Mode
    • Integrated High-bandwidth Digital Content Protection (HDCP) version 1.4
    Block Diagram -- eDP 1.4 Receiver
  • eDP 1.4 Transmitter
    • Compliant with Embedded DisplayPort 1.4 specification
    • Main Link supports 1, 2 or 4 lanes at 1.62Gbps, 2.7Gbps and 5.4Gbps
    • 4 channel S/PDIF Digital Audio Input
    • Supports Enhanced Framing Mode
    Block Diagram -- eDP 1.4 Transmitter
  • eDP1.4 Transmitter PHY
    • Area: 0.572mm2 (1040um x 550um) including IO and ESD
    • Compliant with DP1.2 and eDP1.4 specification
    • Typical 27MHz reference clock
    • Support 1/2/4-lane configuration
  • DP/eDP1.4/1.2 TX PHY&controller
    • Area: 0.75mm2 with pixel PLL and 0.63mm2 without pixel PLL including IO and ESD
    • Compliant with DP1.4 and eDP1.4specification
    • Typical 27MHz reference clock
    • Supports 1/2/4-lane configuration
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