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eDP IP

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Search (46)
Compare 46 IP from 18 vendors (1 - 10)
  • eDP 2.0 Verification IP
    • The eDP 2.0 Verification IP provides an effective & efficient way to verify the components interfacing with the eDP interface of an ASIC/FPGA or SoC.
    • The eDP VIP is fully compliant with the Standard eDP Version 2.0 specifications from VESA.
    • This VIP is a lightweight VIP with an easy plug-and-play interface, so that there is no hit on the design time and the simulation time.
    Block Diagram -- eDP 2.0 Verification IP
  • eDP TRANSMITTER IIP
    • Supports eDP 1.4b specification
    • Supports full eDP Transmitter functionality
    • Supports multi lanes upto 4 lanes.
    • Supports main link, Aux link and Hot plug functionality.
    Block Diagram -- eDP TRANSMITTER IIP
  • eDP RECEIVER IIP
    • Supports eDP 1.4b specification
    • Supports full eDP Receiver functionality
    • Supports multi lanes upto 4 lanes.
    • Supports main link, Aux link and Hot plug functionality.
    Block Diagram -- eDP RECEIVER IIP
  • eDP 1.5 Verification IP
    • Fully compliant with VESA Embedded DisplayPort (eDP) Standard 1.5 Specification
    • Supports power saving feature:- Panel Self Refresh features PSR/PSR2, PR, Adaptive sync, and backlight control.
    • Supports HDCP version 1.4, 2.2 and 2.3
    • Supports Alternative Scrambler Seed Reset (ASSR)
      • TPS4 with ASSR is supported
    Block Diagram -- eDP 1.5 Verification IP
  • eDP PHY
    • Compatible with embedded display port v1.5/v1.4b specification 
    • Four-lane main link with support for 8.1/5.4/4.32/3.24/2.7/2.43/2.16/1.62Gbps 
    • Supports Enhanced Framing Mode 
    • Automatic Link-Training with an option for firmware-controlled Link-Training procedure 
    Block Diagram -- eDP PHY
  • eDP 1.3 Transmitter PHY
    • Fully compliant to VESA Embedded DisplayPort 1.3 specifications
    • Support Embedded DisplayPort RBR, HBR, and HBR2 data rate and customized data rate
    • Configurable x1/x2/x4 Main-Link data lanes
    • PIPE SerDes Mode interface to Embedded DisplayPort controller
  • eDP RX PHY - 14 nm
    • The eDP RX PHY IP is a cost-effective and low-power solution that includes IO pads and ESD structures.
    • With extensive built-in self-test features, including loopback and scan, it ensures robust functionality and easy verification.
    • This hardmacro supports the eDP RX v1.4b and v1.5a standard and is commonly used for connecting a timing controller (TCON) to a host processor.
    Block Diagram -- eDP RX PHY - 14 nm
  • eDP 1.4 Receiver
    • Compliant with Embedded DisplayPort 1.4 specification
    • Support for up to 4 Dual-Speed lanes at 1.62 Gbit/s and 2.7 Gbit/s
    • Supports Enhanced Framing Mode
    • Integrated High-bandwidth Digital Content Protection (HDCP) version 1.4
    Block Diagram -- eDP 1.4 Receiver
  • eDP 1.4 Transmitter
    • Compliant with Embedded DisplayPort 1.4 specification
    • Main Link supports 1, 2 or 4 lanes at 1.62Gbps, 2.7Gbps and 5.4Gbps
    • 4 channel S/PDIF Digital Audio Input
    • Supports Enhanced Framing Mode
    Block Diagram -- eDP 1.4 Transmitter
  • eDP1.4/DP1.3 TX Link IP
    • eDP version 1.4a, DP version 1.3 compliant receiver
    • Supports HDCP Decryption
    • Supports both 1.62/8.1Gbps data rate
    Block Diagram -- eDP1.4/DP1.3 TX Link IP
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