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UHS-II IP

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Compare 14 IP from 7 vendors (1 - 10)
  • UHS-II PHY Core IP
    • The UHS-II PHY IP is a comprehensive, silicon-proven configurable core that has been ported to multiple process nodes and leading foundries.
    • It uses sub-LVDS signaling consisting of one pair each for transmit, receive, and an additional reference clock. This low-pin interface has reduced power consumption and low EMI.
    • To further reduce power, the reference clock operates at 1/15 or 1/30 of the data transfer speed.
    Block Diagram -- UHS-II PHY Core IP
  • UHS-II Device Controller
    • Compliance with Part 1 UHS-II Addendum Version 1.02
    • Compliance with Part A2 SD Host controller specification version 4.10 & Part1 Physical layer specification version 4.20
    • Programmable 1 or 2 Data lane Configuration
    • Supports all type of packets
    Block Diagram -- UHS-II Device Controller
  • SD4.0 / UHS-II Host Controller & PHY
    • + Support Standard Capacity (SDSC), High Capacity (SDHC) and Extended Capacity (SDXC) cards
    • + 1 and 4-bit parallel legacy SD interface, and serial UHS-II interface
    • + All bus interface modes: legacy SD (DS, HS, SDR12, SDR25, SDR50, SDR104, DDR50) and UHS-II (FD156, HD312)
    • + Data transfer rate up to 104 Mbps with 4 parallel SD data lines
  • SD 4.1 Hardware Validation Platform
    • Designed to be cost-effective and Linux based, this SD 4.1 hardware validation platform (HVP) consists of Arasan’s SD4.0 IP mapped into FPGA’s, offering full speed physical connectivity to a complementary SoC host or memory card device.
    Block Diagram -- SD 4.1 Hardware Validation Platform
  • SD 4.1 / SDIO 4.1 / eMMC 4.51 Host Controller IP
    • The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies.
    • SD 4.1 Host Controller IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
    Block Diagram -- SD 4.1 / SDIO 4.1 / eMMC 4.51 Host Controller IP
  • SD 4.1 Device Controller IP
    • Fully compliant core with proven silicon
    • Compliant with SD Specification Part E SD Specification 4.0
    • Transfers up to 300 MB/s (UHS156)
    • Supports Asynchronous Interrupt to Host controller
    • Enhanced power management using new Power
    Block Diagram -- SD 4.1 Device Controller IP
  • SD 4.1 eMMC 5.1 Dual Host Controller IP
    • The SD 4.1/SDIO 4.0/eMMC 5.0 Host IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies:
    • The SD 4.1 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the SD 4.1 / eMMC5.1 Host IP.
    • eMMC 5.1 is backward compatible to the previous versions.
    •  
    Block Diagram -- SD 4.1 eMMC 5.1 Dual Host Controller IP
  • SD Card Controller - Verifies SD card interface functionality, ensuring reliable data transfer and compliance with specifications
    • The SD Card Controller Verification IP (VIP) is a tool designed to ensure the proper functionality and performance of SD card memory interfaces in SoCs. It validates key operations like read/write cycles, error handling, and power management across multiple SD card versions.
    • This VIP is widely applicable in various fields, from SoC design validation to mobile devices and embedded systems. It guarantees reliable data transfer and smooth integration with SD card interfaces in industries such as automotive, consumer electronics, IoT, and more
    Block Diagram -- SD Card Controller - Verifies SD card interface functionality, ensuring reliable data transfer and compliance with specifications
  • Simulation VIP for SD CARD and SDIO
    • SD Card device standard
    • Speed Range A and B
    • Default Speed Range A and faster Range B support
    • PHY-LINK I/F
  • SDIO UHS II Verification IP
    • Supports SD specification UHS-II Adddendum version 2.00 compliant.
    • Supports Part E1 SDIO specification version 4.10.
    • Supports SD specification physical layer version 4.0/4.20/5.0/5.10/6.0/6.10/7.0/7.10/8.0(Draft).
    • Supports bi-directional receiver/transmitter (2ch) supporting both Full Duplex and Half Duplex modes.
    Block Diagram -- SDIO UHS II Verification IP
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