Vendor: Cadence Design Systems, Inc. Category: SD / eMMC Controller

Simulation VIP for SD CARD and SDIO

In production since 2012 for many production designs.SD CARD Cadence Verification IP (VIP) upgrades the SD CARD and SDIO verifica…

Overview

In production since 2012 for many production designs.

SD CARD Cadence Verification IP (VIP) upgrades the SD CARD and SDIO verification platform with Ultra High Speed Type II (UHS-II) support. It allows seamless verification of legacy SD CARD and SDIO protocol (version 3.00 and below) and the latest UHS-II interface. The UHS-II interface allows access to traditional SD CARD and SDIO applications through the SD-TRAN layer and to the UHS-II memory space through the CM-TRAN layer. The VIP allows full-stack UHS-II interface verification (TRAN + LINK + PHY) through the serial interface and protocol IP verification (stripped of PHY) through the PHY-LINK I/F defined in the specification.

SD Host Controller Cadence Verification IP (VIP) is based on Part E1 SDIO (SD input/output) specification defined for SD and SPI bus interface specification for SDIO including register specification. It is defined for SDIO Card, Embedded SDIO device, and Combo Card.

Supported specifications:

For SD CAR – Part 1 Physical Layer Specification Version 4.00 and Part 1 UHS-II Addendum Version 1.00

For SD Host Controller – SD Specifications Part E1 SDIO Simplified Specification Version 3.00 and Part 1 Physical Layer Specification Version 3.01.

Key features

  • SD Card device standard
  • Speed Range A and B
    • Default Speed Range A and faster Range B support
  • PHY-LINK I/F
    • Interface defined in Appendix-F allows verification of protocol IP independently
  • Half-duplex
    • Half-duplex (2L-HD) mode of operation that doubles data throughput
  • Data Bust Streaming
    • Allows multiple model instances to be connected using ring connection
  • Data Burst Retry
    • Data Burst Retry support through the simulation of recoverable error
  • Embedded Flash
    • Support of an embedded flash as defined in eSD specification
  • Area
    • Support of the boot area, user area, and other partition through CMD43 and
  • Fast Boot
    • Support of fast boot feature
  • Boot Code Loading
    • Boot code can be loaded from one of the model instances designated as boot device
  • Low Power Mode
    • Low Power Mode supported through configuration register setting
  • SD Host Controller standard
  • Multiple Modes
    • Supports both SD mode and SPI mode
  • Multi-function
    • Supports IO only, Memory only, and IO+Memory
  • UHS-I
    • Supports UHS-I initialization and transmission
  • Bus width
    • 1-bit mode and 4-bit mode (SD Mode only)
  • Initialization
    • IO Aware and Non-IO Aware initialization sequences for both SD and SPI modes
    • Supports auto initialization and manual initialization
  • Multi Block Read/Write
    • For both IO and memory commands. Busy signaling supported with write commands for SD and SPI
  • Clock Stop and Voltage Switching
    • Clock stop and voltage switching command support
  • Read Wait and Suspend Resume
    • Read wait and suspend and resume functionality
  • Abort
    • Data transfer abort for both IO and memory
  • Dynamic Reset
    • Dynamic reset commands
  • CARD Interface Register Access
    • Commands to access card interface fixed registers

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
Simulation VIP for SD CARD and SDIO
Vendor
Cadence Design Systems, Inc.

Provider

Cadence Design Systems, Inc.
HQ: USA
If you want to achieve silicon success, let Cadence help you choose the right IP solution and capture its full value in your SoC design. Cadence® IP solutions offer the combined advantages of a high-quality portfolio, an open platform, a modern IP factory approach to quality, and a strong ecosystem. Now you can tackle IP-to-SoC development in a system context, focus your internal effort on differentiation, and leverage multi-function cores to do more, faster. The Cadence IP Portfolio includes silicon-proven Tensilica® IP cores, analog PHY interfaces, standards-based IP cores, verification IP cores, and other solutions as well as customization services for current and emerging industry standards. The Cadence IP Factory provides you with an automated approach to the customization, delivery, and verification of SoC IP. As a result, you can spend more time on differentiation, with the assurance that you'll meet your performance, power, and area requirements. Choosing Cadence IP enables you to design with confidence because you have more freedom to innovate your SoCs with less risk and faster time to market.

Learn more about SD / eMMC Controller IP core

Types of Storages for Computing System-On-Chips

We are living in an age where we generate the same amount of data each year that has been generated since antiquity. Ever wondered how and where these peta /exa/zetta bytes of data are stored?

Virtual Prototyping Platform with Flash Memory

In this paper we will see how the flash memories developed using Carbon Model Studio helps to bring up an ARM® Cortex A7 flash memory sub-system with primary and secondary boot codes. Flash memories system demonstrated here can be used for early boot code and driver development for any CPU based SoC.

UFS Goes Mainstream

UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.

Universal Flash Storage: Mobilize Your Data

Universal Flash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniProSM as well as eMMC form factors to simplify adoption and development.

Frequently asked questions about SD / eMMC Controller IP cores

What is Simulation VIP for SD CARD and SDIO?

Simulation VIP for SD CARD and SDIO is a SD / eMMC Controller IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this SD / eMMC Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SD / eMMC Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP