IP Catalog > Memory Controller/PHY IP > SD/eMMC IP > SD/eMMC Controller IP > SD 4.1 Device Controller IP

SD 4.1 Device Controller IP

Overview

The SD 4.1 Device Controller IP core is used to implement SD cards that are connected to a Host processor over a standard SD bus. The SD 4.0 Device IP core is fully compliant with the SD specification. It supports the dual row pin memory cards with D0+/D0- and D1+/D1- pins for differential signaling.

It also supports SPI, SD1, and SD4 bit transfer modes, and multiple functions per card. High-speed and full-speed SD data transfers are also supported to capacities up to 2TB. All version 4.0 features are supported including the UHS-II PHY, SDHS, mini-SD, embedded SD ATA standard function interface code, and extended 2.7-3.6V operating voltages. The SD 4.1 Device Controller includes a bidirectional FIFO that is expandable from 4 x 32-bit to any size required.

The core supports asynchronous interrupts to the Host processor for improved performance. It supports suspend/resume operation for improved performance. The controller integrates a scatter-gather DMA engine automating data transfers between the SD card and system memory.

The SD 4.1 Device Controller IP core is available with several system bus interfaces including AHB, AXI, OCP, Avalon, BVCI, SPI and custom buses.

Key Features

  • Fully compliant core with proven silicon
  • Compliant with SD Specification Part E SD Specification 4.0
  • Transfers up to 300 MB/s (UHS156)
  • Supports Asynchronous Interrupt to Host controller
  • Enhanced power management using new Power State Control function
  • Supports Read Wait Control, Suspend/Resume operations for superior card performance
  • High-performance UHS-II PHY or UHS-I Host connection
  • Multiple I/O functions and one memory supported
  • Host clock rate from 0 to 208 MHz (SDR 104)
  • Supports SPI, 1-bit, and 4-bit SD modes.
  • Optional 8-bit mode for embedded SD
  • Supports all SD form factors including standard, mini and micro SD card
  • Embedded SD ATA interface code
  • Bus Master with Scatter Gather DMA
  • Dual operating voltage range 2.7V – 3.6V and 1.7V – 1.95V
  • Maximum 104 MB/s read/write with 4-bit data lines in SD4 mode
  • CRC7 (command), CRC16 (data) integrity
  • Supports direct R/W (IO52) and extended R/W (IO53)

Benefits

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  • Fully compliant core with proven silicon
  • Premier direct support from Arasan IP core designers
  • Easy-to-use industry standard test environment
  • Unencrypted source code allows easy implementation
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  • Customer training available
  • Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured using Spyglass
  • UHS_II PHY or UHS-I Synthesizable Interface
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Block Diagram

SD 4.1 Device Controller IP Block Diagram

Deliverables

  • RMM-compliant synthesizable RTL design in Verilog
  • Easy-to-use test environment
  • Synthesis scripts
  • Technical documents

Technical Specifications

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