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Compare 80 IP from 28 vendors (1 - 10)
  • 100G UDP IP Stack
    • 100G Ethernet
    • IPv4 support without packet fragmentation
    • Jumbo Frames
    • Transmit and Receive
    • ARP with Cache
    • ICMP (Ping Reply) UDP Unicast
    Block Diagram -- 100G UDP IP Stack
  • 1G UDP IP Stack
    • Supports 1G Ethernet packet processing.
    • UDP Port Filtering based on port numbers.
    • Address Resolution Protocol (ARP) is supported.
    • IP Header Checksum Validation.
    Block Diagram -- 1G UDP IP Stack
  • 10G UDP IP Stack
    • 10G Ethernet
    • IPv4 support without packet fragmentation
    • Jumbo Frames
    • Transmit and Receive
    • ARP with Cache
    • ICMP (Ping Reply)
    Block Diagram -- 10G UDP IP Stack
  • 40G UDP IP Stack
    • 40G Ethernet
    • IPv4 support without packet fragmentation
    • Jumbo Frames
    • Transmit and Receive
    Block Diagram -- 40G UDP IP Stack
  • UDP 100G / 40G / 25G / 10G / 1G IP core
    • UDP100G/40G/25G/10G/1G IP core is the epochal solution implemented without CPU.
    • This IP core is suitable for network application.
    • This IP product includes reference design for AMD FPGA. It helps you to reduce development time.
    Block Diagram -- UDP 100G / 40G / 25G / 10G / 1G IP core
  • Ethernet IP Core compliant with 100BASE-TX and 1000BASE-T
    • The Ethernet IP Core is compliant with 100BASE-TX and 1000BASE-T, supporting all commonly used PHY interfaces like MII, GMII, RGMII and SGMII.
    • Thanks to its built-in DMA capabilities and the wide variety of high-speed interfaces (AXI/AXI Lite and AHB/APB bus), the IP Core can be coupled with a microprocessor to handle TCP/IP packets.
  • eCPRI Altera® FPGA IP
    • The enhanced Common Public Radio Interface (eCPRI) Altera® FPGA IP core implements the eCPRI specification version 2.0
    • It is a front-haul interface protocol for radio base stations aimed at connecting the eCPRI Radio Equipment Control (eREC) and the eCPRI Radio Equipment (eRE) via front-haul transport network.
    Block Diagram -- eCPRI Altera® FPGA IP
  • Intel® Agilex™ 7 F-Tile Ethernet Hard IP
    • The Intel® Agilex™ 7 FPGA F-Tile incorporates a fracturable, configurable, hardened Ethernet protocol stack for supporting rates from 10G to 400G, compatible with IEEE 802.3 specification, and other related Ethernet Consortium specifications.
    Block Diagram -- Intel® Agilex™ 7 F-Tile Ethernet Hard IP
  • Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile Hard IP
    • The Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible with the IEEE 802.3 High-Speed Ethernet Standard and the 25G and 50G Ethernet Specification, Draft 1.6 from the 25G Ethernet Consortium
    • The Intellectual Property (IP) core provides access to this hard IP at data rates of 10 Gbps, 25 Gbps, and 100 Gbps.
    Block Diagram -- Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile Hard IP
  • DiFi IP core
    • The DiFi IP core is a highly scalable and silicon agnostic implementation of the IEEE-ISTO Std 4900-2021: Digital IF Interoperability Standard v1.2.1 targeting ASIC, and FPGA technologies.
    • The DiFi implementation builds on long-time experience designing IP cores for sending and receiving Radio IQ data over Ethernet networks, and delivers a flexible engine that is prepared for tight integration with software applications.
    Block Diagram -- DiFi IP core
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Semiconductor IP