The Ethernet IP Core is compliant with 100BASE-TX and 1000BASE-T, supporting all commonly used PHY interfaces like MII, GMII, RGMII and SGMII. Thanks to its built-in DMA capabilities and the wide variety of high-speed interfaces (AXI/AXI Lite and AHB/APB bus), the IP Core can be coupled with a microprocessor to handle TCP/IP packets. The IP Core can generate and receiving UDP packets without the need for microprocessor intervention. In order to reduce the number of incoming packets and CPU workload, the design features MAC filtering capability. This feature can be disabled to enable promiscuous mode, allowing the analysis of all packets in the network.
SPECIFICATIONS
| Supported Interfaces | MII, GMII, RGMII, SGMII |
| Configuration bus protocol | Axi Lite / APB |
| Supported OS | Linux, RTEMS, FreeRTOS |
| MAC Filtering | Yes |
| UDP | Standalone implementation |
| TCP/IP | Software implementation |
| Data bus protocols | AXI/AHB |
| ARP resolution | Yes |