RISC-V 32-Bit CPU IP

Filter

Compare 36 IP from 7 vendors (1 - 10)

32-bit RISC-V CPU with M, Zicsr extensions, and External Debug support
- Five-stage pipeline
- Harvard architecture
- RV32I Base RISC-V ISA
Ultra Compact 32-bit RISC-V CPU Core
- AndeStar™ V5/V5e Instruction Set Architecture (ISA)
- Compliant to RISC-V technology
- Support RV32IMAC/EMAC
ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
- D23-SE processor core certified by parts 2, 4, 5, 7, 8 and 9 of the standards, meeting the architectural metrics and random hardware fault metrics requirements for ASIL B/D
- D23-SE supports split-mode that 2 cores could run independently when split-lock is configured. ECC for memory soft error protection; bus protection to protect bus transaction; core trap status bus interface provides real time information of trap status from core.
32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications
- 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications
ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
- 32-bit RISC-V embedded CPU with balanced 3-stage pipeline
- DSP implementation to extend the RISC-V baseline (RMX-100D)
- 2 KB to 64 KB instruction L1 cache
- Up to 2MB instruction and data closely coupled memory (CCM)
ARC-V RHX-105 dual-issue, 32-bit RISC-V processor for real-time applications (multi-core)
- High-speed, 32-bit, dual-issue, 10-stage pipeline
- Multicore support for up to 16 CPUs and up to 16 user hardware accelerators per processor cluster
ARC-V RMX-500 power efficient 32-bit RISC-V processor for embedded applications
- 32-bit RISC-V embedded CPU with a 5-stage pipeline
- DSP implementation to extend the RISC-V baseline (RMX-500D)
- 2 KB to 64 KB instruction & data L1 caches
Compact and Performance Efficiency 32-bit RISC-V Core
- AndeStar™ V5 Instruction Set Architecture (ISA)
- Compliant with RISC-V I, M, A, C, B and Zce extensions
- Andes extensions for performance and code size enhancements
Compact, Secure and Performance Efficiency 32-bit RISC-V Core
- AndeStar™ V5/V5e Instruction Set Architecture (ISA)
- Andes extensions for performance and code size enhancements
RISC-V CPU IP With ISO 26262 Full Compliance
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- Bit-manipulation extensions