ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications

Overview

The Synopsys ARC-V™ RMX-100 series processors are optimized for use in embedded applications where power and area are the utmost concern.
The DSP enhanced implementation (RMX-100D) adds DSP capability for applications such as hearable devices where the combination of low power and signal processing are required to enable device performance and extend battery life.
The ARC-V RMX-100 processors are based on the RISC-V instruction set architecture (ISA). The processors feature a balanced 3-stage Harvard architecture pipeline that provides sufficient throughput.
The ARC-V RMX-100 features up to 64KB of level 1 (L1) instruction cache and up to 2MB each of closely coupled instruction and data memories (CCM).
The DSP-enhanced RMX-100D cores include an optimized DSP implementation that features a power-efficient unified 32x32 MUL/MAC unit and support
for fixed-point DSP datatypes and vector operations. To enable easy DSP software development, the ARC MetaWare Development Toolkit features a rich DSP software library and the included C/C++ Compiler supports commonly used DSP datatypes for easy algorithm programming. The ARC-V RMX-
100D processors maintain the high code density and offer excellent DSP performance within a very small footprint.

Key Features

32-bit RISC-V embedded CPU with balanced 3-stage pipeline
DSP implementation to extend the RISC-V baseline (RMX-100D)
2 KB to 64 KB instruction L1 cache
Up to 2MB instruction and data closely coupled memory (CCM)
Architectural clock gating and enhanced sleep instructions
RISC-V S-mode security
RISC-V Memory Protection Unit (ePMP) to control access rights to the memory
ECC / parity support
Integrated watchdog timer
32x32 multiplier / Configurable hardware divider
Advanced Platform Level Interrupt Controller (APLIC) supporting up to 1023 wired interrupts
Up to 2x Advanced Platform Level Interrupt Controllers (APLIC) each supporting up to 1023 wired interrupts for a maximum of 2046 interrupts
DSP support (RMX-100D): Unified MUL-MAC unit; Fractional data type support; Multiple rounding modes
Native Arm AMBA® AXI™, AHB and AHB-Lite™ interfaces
JTAG and Compact JTAG (cJTAG) debug interface

Benefits

RISC, and RISC + DSP 32-bit processors for ultra-low power embedded apps
Based on the RISC-V ISA, leveraging standard 32-bit protocols (and extensions)
DSP instruction extensions (RMX-100D)
Easy DSP programming support with Synopsys Metaware C/C++ Compiler
Feature-rich DSP software library for easy algorithm programming
High degree of configurability
Support for custom instructions
Support for up to 2 MB of closely coupled memory and direct mapping of peripherals
Native Arm AMBA® AHB™, AHBLite™ and AXI interfaces
Optional 32x32 or 16x16 single and multicycle multiplier
ECC/Parity support
RISC-V AIA compatible interrupt handling architecture
ARC Trace I/F provides real-time trace debugging features

Applications

Industrial: Motor control, smart metering
Automotive: Sensors, keyless entry, body electronics, safety management
Consumer: AIoT, hearables
Storage: consumer SSDs, eMMC, UFS, SD cards
Networking: LPWAN, M2M, BLE control, wireless access (WAP)

Deliverables

The Synopsys ARC-V RMX-100 processors are delivered in Verilog HDL in the ARChitect IP Library. The HDL is configurable by the user and output from the ARChitect IP Configurator tool. To test that the product performs as expected, a basic testbench of Customer Confidence Tests (CCT) is included.

Technical Specifications

Maturity

Available on request

Availability

Available

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