RISC-V CPU IP With ISO 26262 Automotive Functional Safety Compliant

Overview

AndesCore™ N25F-SE is a 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications. Approved based on the functional safety assignments of a Safety Element Out-of-Context (SEooC), which includes the ISO 26262 compliant development process and the qualitative approach with respect to hardware safety analysis, N25F-SE is certified to be used in safety-related applications.

Based on AndeStar™ V5 architecture that incorporated RISC-V technology, N25F-SE is capable of delivering high per-MHz performance and operating at high frequencies with small gate count. It supports single and double precision floating point instructions, branch prediction for efficient branch execution, Instruction and Data caches, local memories for low-latency accesses, and ECC for memory error protection. Features also includes RISC-V Platform Level Interrupt Controller, AXI 64-bit or AHB 64/32-bit system bus, WFI mode for low power and power management, and JTAG debug interface. 

Functional Safety

  • For general-purpose control of embedded systems in automotive applications
  • Compliant with ISO 26262:2018 standard parts 2, 4, 5, 8 and 9 for ASIL (Automotive Safety Integrity Level) B
  • Independent assessment and certification by SGS-TÜV Saar GmbH
  • AndesCore™ N25F-SE ISO 26262 compliant certificate

Key Features

  • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
  • Floating point extensions
  • Bit-manipulation extensions
  • Andes extensions, architected for performance and functionality enhancements
  • 32-bit, 5-stage pipeline CPU architecture
  • 16/32-bit mixable instruction format for compacting code density
  • Branch prediction to speed up control code
  • Return Address Stack (RAS) to speed up procedure returns
  • Physical Memory Protection (PMP)
  • Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
  • Interrupt handling for real-time performance
  • Patented CoDense™ technology to further reduce code size

Block Diagram

RISC-V CPU IP With ISO 26262 Automotive Functional Safety Compliant Block Diagram

Applications

  • Networking and Communications
  • Advanced Driver-Assistance Systems
  • Video and Image Processing
  • Storage and Media Streaming

Technical Specifications

Short description
RISC-V CPU IP With ISO 26262 Automotive Functional Safety Compliant
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Semiconductor IP