RISC IP
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High-performance 32-bit RISC CPU
- 32-bit RISC architecture
- 16 or 32 general purpose registers
- 104 basic instructions and 10 addressing modes
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Compact, low-power 32-bit RISC CPU
- 32-bit RISC architecture
- 16 or 32 general purpose registers
- 104 basic instructions and 10 addressing modes
- Optional IEEE 754 floating point unit (FPU)
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Low-power, 16-bit RISC CPU with cache
- 16-bit RISC architecture
- 16 or 32 general purpose registers
- 92 basic instructions and 10 addressing modes
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Low-cost & low-power 16-bit RISC CPU
- 16-bit RISC architecture
- 16 or 32 general purpose registers
- 92 basic instructions and 10 addressing modes
- Supports up to 74 user-defined instructions
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DSP-enhanced ARC EMxD and HS4xD processors provide combined RISC + DSP processing for computation intensive applications
- ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
- ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
- Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
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32-bit High Performance Single/Multicore RISC System-on-Chip with code compression
- High Performance 32-bit RISC CPU
- Proprietary 6-stage pipeline
- 16-bit code compression
- Single or multicore implementation
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32-bit High Performance Single/Multicore RISC Processor with code compression
- High Performance 32-bit RISC CPU
- Proprietary 6-stage pipeline
- 16-bit code compression
- Single or multicore implementation
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32-bit High Performance Single/Multicore RISC System-on-Chip
- High Performance 32-bit RISC CPU
- Proprietary 6-stage pipeline
- Single or multicore implementation
- Up to 1.37 DMIPS/MHz/Core
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32-bit High Performance Single/Multicore RISC Processor
- High Performance 32-bit RISC CPU
- Proprietary 6-stage pipeline
- Single or multicore implementation
- Up to 1.37 DMIPS/MHz/Core
