32-bit High Performance Single/Multicore RISC Processor with code compression
Overview
The CC150-C processor is a synthesisable Verilog model of a high performance 32-bit RISC processor. The model is highly configurable, and particularly suitable for system-on-a-chip (SoC) designs. The core is interfaced using the AMBA AHB, AHB-Lite and APB buses or AXI4 and AXI4-Lite buses. The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.
Key Features
- High Performance 32-bit RISC CPU
- Proprietary 6-stage pipeline
- 16-bit code compression
- Single or multicore implementation
- Up to 1.37 DMIPS/MHz/Core
- Up to 2.29 CoreMark/MHz/Core
- Optional set-associative caches with data snooping
- Power-down mode
- On-chip debug support
- FPGA and silicon proven
- JTAG or 2-pin Serial Wire Debug
Benefits
- Synthesizable RTL Verilog source code
- Cycle accurate simulator
- Custom instruction set extension
- Mature free GNU-Based C/GDB toolchain
- Full implementation and maintenance support with individual approach
- Low-cost and flexible licensing
- Embedded solution for low-power and low-footprint applications
- Suitable for mobile, IoT and wearable devices
Block Diagram
Technical Specifications
Availability
Now
UMC
Silicon Proven:
130nm
Related IPs
- 32-bit High Performance Single/Multicore RISC System-on-Chip with code compression
- 32-bit RISC Processor To Deliver High Performance In Low-Cost Microcontroller Applications
- 32-bit High Performance Single/Multicore RISC System-on-Chip
- High performance 32-bit RISC-V Processor
- 32-bit RISC-V High Performance Microcontroller Class Processor
- Highest code density, Low Power 32-bit Processor with optional DSP