Low-cost & low-power 16-bit RISC CPU

eSi-RISC's eSi-1600 16-bit RISC CPU IP core is an extremely small, low-cost and low-power processor ideal for integration into ASIC and/or FPGA designs. It offers similar performance to more expensive 32-bit CPUs, while having a system cost comparable to that of 8-bit CPUs. Significant power savings are possible compared to 8-bit CPUs as applications require far fewer clock cycles to run.

Even though it is 16-bit, the gate count is equivalent to many 8-bit cores due to the simplicity of the RISC pipeline. With a wider datapath and 16 general purpose registers, application programs are able to execute in far fewer clock cycles. This can save a significant amount of power by either allowing the CPU to be clocked at a lower frequency or by being able to enter a power down state sooner.

For applications where high performance is required, the 5-stage pipeline allows for high clock frequencies to be achieved even in mature processes.

The eSi-1600’s instruction set includes a variety of arithmetic instructions such as a full 32-bit multiply, multiply and accumulate and divide. There are also a number of optional application specific instructions and addressing modes. Bit manipulation instructions such as bitfield extract and insert, count leading zeros, population count, find first set and bit reverse can be included. Integer square root, absolute value, min/max, CRC and parity are also available. Wait-for-interrupt instructions allow fast entry to low power states, enabling clock and power gating.

For those applications that require extreme performance or ultra low power operation, user-defined instructions and registers can be implemented.

Instructions are encoded in either 16 or 32-bits, with all of the commonly used instructions being encoded in 16-bits, maximizing code density and minimizing instruction fetch power consumption.

The processor supports both user and supervisor operating modes, with privileged instructions and memory areas via the optional MPU, to allow an O/S kernel to be fully protected from user applications.

Hardware debug facilities include hardware breakpoints, watchpoints, trace, performance counters, null pointer detection and single-stepping for fast debugging of ROM, FLASH and RAM based programs.