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Network-on-Chip IP

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Compare 11 IP from 7 vendors (1 - 10)
  • Smart Network-on-Chip (NoC) IP
    • Smart NoC automation
    • Topology generation with minimum wire length
    • Scripting-driven regular topology creation
    • Incremental design capability
    • Auto-timing closure assist
    Block Diagram -- Smart Network-on-Chip (NoC) IP
  • Coherent Network-on-Chip (NoC)
    • External interface protocols: ACE4, ACE5 and CHI
    • Architected to significantly reduce routing congestion for many-core systems
    • Integrated with SkyeChip’s Home Agent and swappable with any other proprietary coherency handlers
    • Supports operating frequencies up to 2GHz with assists in high frequency timing closures
  • Non-Coherent Network-on-Chip (NoC)
    • External Interface Protocols: AXI4, AXI5, AXI-Stream, APB and proprietary protocols
    • Architected to reduce routing congestion and to ease high frequency timing closure
    • Supports operating frequencies up to 2GHz
    • Supports source synchronous and synchronous clocking topologies
  • Network-on-Chip (NoC) Interconnect IP
    • AMBA AXI / APB / AHB protocol compliant
    • Configurable number of masters and slaves
  • Coherent Network-on-chip (NoC) IP
    • Layered, scalable, configurable, and physically aware configurable NoC
    Block Diagram -- Coherent Network-on-chip (NoC) IP
  • Non-coherent Network-on-chip (NoC) IP
    • Layered, scalable, physically aware configurable NoC
    Block Diagram -- Non-coherent Network-on-chip (NoC) IP
  • Ncore 3 Coherent Network-on-Chip (NoC)
    • Supports multiple coherent agents, including Armv9 and RISC-V CPU clusters
    • AMBA CHI-E, CHI-B and ACE interoperability, as well as ACE-Lite and AXI
    • Low-latency proxy caches for efficient and quick integration of hardware accelerators into the coherent domain
    • Configurable last-level caches
    Block Diagram -- Ncore 3 Coherent Network-on-Chip (NoC)
  • HBM Memory Controller
    • Low latency, high bandwidth
    • Supports HBM or DDRx memory types
    • 16 parallel access channels
    • Multi, independent internal queues
    Block Diagram -- HBM Memory Controller
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar
  • Tessent NoC Monitor
    • Full transaction and trace-level visibility of traffic
    • Wide range of measurements, analytics statistics: transactions, bus cycles, latency, duration, beats, concurrency
    Block Diagram -- Tessent NoC Monitor
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Semiconductor IP