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Network-on-Chip IP

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Compare 15 IP from 10 vendors (1 - 10)
  • Smart Network-on-Chip (NoC) IP
    • Smart NoC automation
    • Topology generation with minimum wire length
    • Scripting-driven regular topology creation
    • Incremental design capability
    • Auto-timing closure assist
    Block Diagram -- Smart Network-on-Chip (NoC) IP
  • Network-on-Chip (NoC) Interconnect IP
    • AMBA AXI / APB / AHB protocol compliant
    • Configurable number of masters and slaves
  • Coherent Network-on-chip (NoC) IP
    • Layered, scalable, configurable, and physically aware configurable NoC
    Block Diagram -- Coherent Network-on-chip (NoC) IP
  • Non-coherent Network-on-chip (NoC) IP
    • Layered, scalable, physically aware configurable NoC
    Block Diagram -- Non-coherent Network-on-chip (NoC) IP
  • Coherent Network-on-Chip (NOC)
    • Node Protocols: ACE4, ACE5 and CHI
    • Architected to significantly reduce routing congestion for many-core systems
    • Integrated with SkyeChip’s Home Agent and swappable with any other proprietary coherency handlers
    • Supports operating frequencies up to 2GHz with assists in high frequency timing closures
  • Non-Coherent Network-on-Chip (NOC)
    • Node Protocols: AXI4, AXI5, AXI-Stream, APB and proprietary protocols
    • Architected to reduce routing congestion and to ease high frequency timing closure
    • Supports operating frequencies up to 2GHz
    • Supports source synchronous and synchronous clocking topologies
  • Ncore 3 Coherent Network-on-Chip (NoC)
    • Supports multiple coherent agents, including Armv9 and RISC-V CPU clusters
    • AMBA CHI-E, CHI-B and ACE interoperability, as well as ACE-Lite and AXI
    • Low-latency proxy caches for efficient and quick integration of hardware accelerators into the coherent domain
    • Configurable last-level caches
    Block Diagram -- Ncore 3 Coherent Network-on-Chip (NoC)
  • CXL 3.0 Controller
    • The CXL Controller IP is micro-architected with power, performance, and area optimization for high bandwidth, minimum latency, and low power applications.
    • The CXL IP supports seamless transition from FPGA prototyping to production silicon implementation.
    • Featuring native integration with SignatureIP's Coherent and Non-coherent Network-on-Chip (NoC) IPs, this controller enables robust SoC subsystems and complete platform solutions
    Block Diagram -- CXL 3.0 Controller
  • High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, a VPU, cache coherency, and a hypervisor
    • SCR9 is a high-performance, silicon-proven, Linux-capable 64-bit RISC-V processor core for entry-level server-class applications and personal computing devices.
    • The SCR9 core supports RISC-V standard "I" Integer, "M" Integer Multiplication and Division, "A" Atomic, "C" 16-bit Compressed, "F" Single-Precision Floating-Point, "D" Double-Precision Floating-Point, "V" Vector Operations, "B" Bit Manipulation, and "K" Scalar Cryptography extensions.
    Block Diagram -- High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, a VPU, cache coherency, and a hypervisor
  • HBM2E and HBM2 FPGA IP
    • HBM2E and HBM2 are high-performance memory IPs that offer a combination of high memory bandwidth, low power consumption, low latency, and small form factor for Agilex™ 7 FPGA M-Series and Stratix® 10 MX FPGAs, respectively
    • HBM2E and HBM2 are well-suited for a variety of high-performance computing applications.
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