Smart Network-on-Chip (NoC) IP

Overview

Revolutionizing SoC Design with Intelligent Automation

FlexGen™ redefines how SoC designers create Network-on-Chip IP by introducing cutting-edge AI heuristics and machine learning. This revolutionary IP automates NoC topology generation, achieving up to 10x faster design iterations than traditional methods.

With FlexGen, teams can optimize wire length, reduce latency, and improve power efficiency while minimizing manual intervention. Designed for automotive, data centers, and industrial electronics applications, FlexGen shortens design cycles, enabling faster time-to-market and/or multiple design explorations for the most complex systems.

Efficient Transport of Data Through the SoC

Arteris CodaCache® last-level cache

  • Ideal for NoC applications with data re-use
  • Improves overall SoC latency and power

NoC Integration Automated Flow

Automated flow to leverage SoC connectivity information:

  • Improved productivity with reduced process
  • Better quality with early errors detections thanks to the checkers

Key Features

  • Smart NoC automation
  • Topology generation with minimum wire length
  • Scripting-driven regular topology creation
  • Incremental design capability
  • Auto-timing closure assist
  • … plus all the key features of FlexNoC 5

Benefits

  • 10x Productivity Boost
    •   Smart NoC generation is 10x faster than traditional NoC flows, shortening SoC or chiplet iterations from weeks to days for design efficiency.
  • Expert Level Results
    •   3x improvement in engineering efficiency with expert quality of results with minimal effort across all NoCs. Algorithms minimize routing congestion, improving silicon area during physical design, with proven links to physical synthesis and place and route to support tapeout success.
  • Wire Length Reduction Driven Performance
    •   Smart AI heuristics using machine-learning technology delivers an optimized topology with an average wire length reduction of up to 30%, reducing overall latency by up to 10%, plus power improvements across the design.

Block Diagram

Smart Network-on-Chip (NoC) IP Block Diagram

Technical Specifications

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Semiconductor IP