The CXL Controller IP is micro-architected with power, performance, and area optimization for high bandwidth, minimum latency, and low power applications. The CXL IP supports seamless transition from FPGA prototyping to production silicon implementation. Featuring native integration with SignatureIP's Coherent and Non-coherent Network-on-Chip (NoC) IPs, this controller enables robust SoC subsystems and complete platform solutions.
System Integration:
The CXL Controller IP offers extensive system integration flexibility:
- Direct NoC Integration: Native connectivity with SignatureIP's NoC solutions
- AMBA Ecosystem Compatibility:
- SFI to AXI Bridge provides seamless interface to AMBA AXI-based systems
- CPI to CHI Bridge enables coherent connectivity to AMBA CHI-based systems
- PHY Options: Compatible with industry-standard PIPE and custom SERDES interfaces
- Configuration Options: Multiple configurability options via parameters
- Fabric Management:
- Comprehensive fabric discovery and enumeration
- Dynamic resource allocation and Quality of Service (QoS) management
- Flexible topology configuration with support for heterogeneous devices
- Memory Pooling Architecture:
- Memory device sharing among multiple hosts
- Dynamically adjustable memory allocation based on workload demands
- Support for volatile and non-volatile memory combinations
- Specification Compliance: Full compliance with CXL 3.0 with backward compatibility to 2.0 and 1.1
- Implementation Targets: Optimized for both FPGA and ASIC implementations
- Protocol Support: Complete implementation of CXL.cache, CXL.mem, and CXL.io
- Device Support: Comprehensive support for CXL Type 1, Type 2, and Type 3
- Configuration Modes: Flexible Host, Device, and Dual mode operation
- Application Interfaces:
- Native industry-standard CPI and SFI protocol support
- Seamless connectivity to AMBA-based systems via:
- SFI to AXI Bridge for non-coherent AMBA AXI systems
- CPI to CHI Bridge for coherent AMBA CHI systems
- PHY Integration: Multiple options via PIPE and SERDES interfaces
- Lane Configurations: Supports x1, x4, x8, x16 lanes
- Protocol Flexibility: Advanced alternate protocol negotiation
- Power Management: Comprehensive support for ASPM, L0p, L1.x, Sleep_L2, and DAPM
- System Features: Port bifurcation and config TLP bypass support.
Advanced CXL 3.0 Capabilities:
- High Bandwidth Performance: Supports 64 GT/s data rate (double that of CXL 2.0) with no added latency
- Fabric Architecture Support:
- Multi-level switching enabling non-tree topologies (mesh, ring, spine/leaf)
- Support for up to 4,096 addressable fabric nodes
- Port-based routing for efficient network traversal
- Enhanced Memory Capabilities:
- Global Fabric Attached Memory (GFAM) support for memory pooling
- Memory sharing across multiple compute domains
- Fine-grained resource allocation
- Advanced Coherency Features:
- Peer-to-peer (P2P) direct memory access
- Device-to-device direct communication without host CPU involvement
- Optimized coherent memory sharing between heterogeneous devices
- Flexible Topologies:
- Multiple Type 1 and Type 2 devices per CXL root port
- Dynamic reconfiguration of resources
- Multiple switch layers for complex system architectures
