SkyeChip's NoC is the first in the world that is able to reconfigure routing paths after tapeout. It is a scalable and area efficient interconnect solution optimized for memory coherent systems.
SkyeChip’s Coherent Network-on-Chip (NoC) IP works together with SkyeChip’s Resource and Performance Tuner (RAPTuner ™) to deliver system-optimized interconnect solutions that is used in the construction of ASICs, SoCs, FPGAs and ASSPs.
Coherent Network-on-Chip (NoC)
Overview
Key Features
- External interface protocols: ACE4, ACE5 and CHI
- Architected to significantly reduce routing congestion for many-core systems
- Integrated with SkyeChip’s Home Agent and swappable with any other proprietary coherency handlers
- Supports operating frequencies up to 2GHz with assists in high frequency timing closures
- Supports source synchronous and synchronous clocking topologies
- Integrates seamlessly with SkyeChip’s Coherent NoC for partitioned interconnect systems
Benefits
- Configurability & Debug
- RAPTuner™ Design Suite integrated with SystemC simulator
- Highly Scalable with Modular sub-NoC
Deliverables
- RAPTuner ™ software
- Software user manual
- NoC IP core
- Documentation
Technical Specifications
Availability
Since April 2024