Mobile pcie IP

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array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "" "category.id" => array:1 [ 0 => 319 ] "category.name" => array:1 [ 0 => "PCI Express Controller IP" ] "category.slug" => [] "created_at" => 1757945168 "id" => "23759" "keyfeatures" => """ Compliant with the following specifications:\r\n \r\n <ul>\r\n \t<li>AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0</li>\r\n \t<li>AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0</li>\r\n \t<li>AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0</li>\r\n \t<li>AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0</li>\r\n </ul>\r\n \r\n DTI PCIe Controller supports:\r\n \r\n <ul>\r\n \t<li>Master only operation</li>\r\n \t<li>Slave only operation</li>\r\n \t<li>Master and slave operation</li>\r\n \t<li>Clock synchronization</li>\r\n \t<li>Programmable FIFO watermarks</li>\r\n \t<li>Interrupt interface</li>\r\n </ul> """ "keyfeatures_cn" => "" "keywords" => "" "logo" => "dolphinic-66bb47735e1d5.webp" "logo2" => "dolphinic-66bb47735e1d5.webp" "name" => "asic.node" "overview" => """ Dolphin PCIe Controller is a high-performance and compact solution for PCIe provide high-throughput, low-latency, and power-efficient external connectivity in SoCs for mobile, networking, storage, cloud computing, and automotive applications. \r\n \r\n The PCIe Controller consists of silicon-proven digital controllers, PHYs and verification IP, all of which are designed to support all required features of the PCIe 5.0 32GT/s (Gen5), PCIe 4.0 16GT/s (Gen4), 3.1 8GT/s (Gen3), 2.1 5GT/s (Gen2) and 1.1 2.5GT/s (Gen1). """ "overview_cn" => "" "partnumber" => "PCIe Controller" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 139 "provider.name" => "Dolphin Technology" "provider.object" => "{"id":139,"name":"Dolphin Technology","providerslug":"dolphin-technology"}" "provider.priority" => 221 "provider.slug" => "dolphin-technology" "published_as_new_at" => 0 "seofeatures" => """ <ul>\r\n \t<li>Dolphin PCIe Controller is a high-performance and compact solution for PCIe provide high-throughput, low-latency, and power-efficient external connectivity in SoCs for mobile, networking, storage, cloud computing, and automotive applications.</li>\r\n \t<li>The PCIe Controller consists of silicon-proven digital controllers, PHYs and verification IP, all of which are designed to support all required features of the PCIe 5.0 32GT/s (Gen5), PCIe 4.0 16GT/s (Gen4), 3.1 8GT/s (Gen3), 2.1 5GT/s (Gen2) and 1.1 2.5GT/s (Gen1).</li>\r\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "PCIe Controller" "shortdescription_cn" => "" "slug" => "pcie-controller-ip-2" "sortable_id" => 23759 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 58 ] "taxo3" => array:1 [ 0 => 430 ] "taxo4" => array:1 [ 0 => 319 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "PCIe Controller Dolphin Technology" "text_low_priority" => """ Dolphin PCIe Controller is a high-performance and compact solution for provide high-throughput low-latency power-efficient external connectivity in SoCs mobile networking storage cloud computing automotive applications.\r\n \r\n The consists of silicon-proven digital controllers PHYs verification IP all which are designed to support required features the 5.0 32GT/s (Gen5) 4.0 16GT/s (Gen4) 3.1 8GT/s (Gen3) 2.1 5GT/s (Gen2) 1.1 2.5GT/s (Gen1). Compliant with following specifications:\r\n \r\n \r\n \tAMBA Advanced Peripheral Bus (APB) Specification Version 2.0\r\n \tAMBA High-performance (AHB) eXtensibale (AXI) 4.0\r\n \tAMBA Lite (AXI-Lite) 4.0\r\n \r\n \r\n DTI supports:\r\n \r\n \r\n \tMaster only operation\r\n \tSlave operation\r\n \tMaster slave operation\r\n \tClock synchronization\r\n \tProgrammable FIFO watermarks\r\n \tInterrupt interface\r\n """ "text_medium_priority" => "" "updated_at" => 1757946996 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ "matched_tokens" => array:1 [ …1] "snippet" => "PCIe Controller Dolphin Technology" ] "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ …1] "snippet" => "Dolphin PCIe Controller is a high-performance" ] ] "highlights" => array:2 [ 0 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:1 [ …1] "snippet" => "Dolphin PCIe Controller is a high-performance" ] 1 => array:3 [ "field" => "text_high_priority" "matched_tokens" => array:1 [ …1] "snippet" => "PCIe Controller Dolphin Technology" ] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 1 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "/upload/catalog/product/blockdiagram/22769/icon_2025-05-02-203723-68151173f201d.png.webp" "category.id" => array:1 [ 0 => 319 ] "category.name" => array:1 [ 0 => "PCI Express Controller IP" ] "category.slug" => [] "created_at" => 1746218387 "id" => "22769" "keyfeatures" => """ <ul>\r\n \t<li>Data transfer rate : PCIe 3.0 supports a data transfer rate of up - to 8 GT / s (gigatransfers per second), which is twice the speed of 2.0.</li>\r\n \t<li>Link width : The link width for PCIe 3.0 is up to 16 lanes, which provides a maximum bandwidth of 15.75 GB / s (gigabytes per second) in each direction.</li>\r\n \t<li>Lane configuration : PCIe 3.0 has the same lane configuration as its predecessor, PCIe 2.0, with up to 16 lanes. Each lane can provide up to 985 MB / s of bandwidth.</li>\r\n \t<li>Increased lane flexibility : PCIe 3.0 also offers increased lane flexibility, allowing the configuration of lanes to be changed dynamically depending on the needs of the system.</li>\r\n \t<li>Backward compatibility : PCIe 3.0 is backward compatible with PCIe 2.0 and PCIe 1.0, meaning that devices designed for earlier PCIe versions can be used with a PCIe 3.0 slot, but at a reduced speed.</li>\r\n \t<li>Multi - function support : PCIe 3.0 supports multi - function devices, which can provide multiple functions through a single physical device, reducing the need for multiple expansion slots.</li>\r\n \t<li>Power consumption : PCIe 3.0 is designed to be more power - efficient than its predecessors, which can help to reduce energy consumption and heat generation.</li>\r\n </ul> """ "keyfeatures_cn" => "" "keywords" => "" "logo" => "siliconcores-66bb476255681.webp" "logo2" => "siliconcores-66bb476255681.webp" "name" => "asic.node" "overview" => """ The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect various components to a computer's motherboard. It is the third generation of the PCIe standard and offers increased bandwidth, improved performance, and reduced power consumption compared to its predecessor, PCIe 2.0 Overall, PCIe 3.0 provides faster and more efficient communication between the various components in a computer, including graphics cards, network adapters, and storage devices, resulting in better overall performance.\r\n \r\n PCIe 3.0 is a high - speed, bidirectional, and low - cost point-to-point interface that is widely used in PC, consumer electronics, and mobile architectures. It supports dynamic attachment of multiple peripherals to the host via a switch or a bridge. PCIe 3.0 is an open architecture that offers higher data throughput and enables the connection of up to 128 devices to a single port on the motherboard. It is a serial protocol and physical link that transmits data differentially on multiple pairs of wires, while simultaneously providing power to the connected peripherals.\r\n \r\n As technology advances, new types of devices, media formats, and storage systems require more bus bandwidth to deliver the desired user experience. In addition, user applications demand faster and more efficient connections between the PC and these increasingly sophisticated peripherals. PCIe 3.0 addresses these requirements by delivering a significantly higher transfer rate that matches the needs of modern usage scenarios and devices. Its increased bandwidth and other features make it an ideal interface standard for meeting the performance demands of modern computer systems.\r\n \r\n Product Specifications :\r\n \r\n <ul>\r\n \t<li>Fully synthesizable Register Transfer Level (RTL) Verilog HDL core</li>\r\n \t<li>Test Bench. (Environment Variable : Verilog)</li>\r\n \t<li>Methodologies - based Test Bench : UVM</li>\r\n \t<li>Fault Simulation done</li>\r\n \t<li>Test Realization in Portable Stimulus Standards (PSS)</li>\r\n \t<li>Targeted to Synopsys® Zebu® EP - 1</li>\r\n </ul>\r\n \r\n Product Options :\r\n \r\n <ul>\r\n \t<li>Adaptations :\r\n \t<ul>\r\n \t\t<li>8 Bit 8051 Microcontroller Interface available.</li>\r\n \t\t<li>16 / 32 Bit Standard Microcontroller Interface possible.</li>\r\n \t\t<li>DMA Functionality possible.</li>\r\n \t</ul>\r\n \t</li>\r\n \t<li>Add - ons : Verification IP - UVM VIP</li>\r\n </ul> """ "overview_cn" => "" "partnumber" => "SI23PCIe30" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 44 "provider.name" => "Silicon Cores - a Div. of Silicon Interfaces" "provider.object" => "{"id":44,"name":"Silicon Cores - a Div. of Silicon Interfaces","providerslug":"silicon-cores-a-div-of-silicon-interfaces"}" "provider.priority" => 1 "provider.slug" => "silicon-cores-a-div-of-silicon-interfaces" "published_as_new_at" => 0 "seofeatures" => """ <ul>\r\n \t<li>The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect various components to a computer's motherboard.</li>\r\n \t<li>It is the third generation of the PCIe standard and offers increased bandwidth, improved performance, and reduced power consumption compared to its predecessor, PCIe 2.0 Overall, PCIe 3.0 provides faster and more efficient communication between the various components in a computer, including graphics cards, network adapters, and storage devices, resulting in better overall performance.</li>\r\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "PCIe - PCI Express Controller" "shortdescription_cn" => "" "slug" => "pcie-pci-express-controller-ip" "sortable_id" => 22769 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 58 ] "taxo3" => array:1 [ 0 => 430 ] "taxo4" => array:1 [ 0 => 319 ] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "SI23PCIe30 PCIe - PCI Express Controller Silicon Cores a Div. of Interfaces" "text_low_priority" => """ The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that used to connect various components computer's motherboard. It the third generation of and offers increased bandwidth improved performance reduced power consumption compared its predecessor 2.0 Overall provides faster more efficient communication between in including graphics cards network adapters storage devices resulting better overall performance.\r\n \r\n PCIe high - speed bidirectional low cost point-to-point widely PC consumer electronics mobile architectures. supports dynamic attachment multiple peripherals host via switch or bridge. an open architecture higher data throughput enables connection up 128 single port on serial protocol physical link transmits differentially pairs wires while simultaneously providing connected peripherals.\r\n \r\n As technology advances new types media formats systems require bus deliver desired user experience. In addition applications demand connections these increasingly sophisticated peripherals. addresses requirements by delivering significantly transfer rate matches needs modern usage scenarios devices. Its other features make it ideal for meeting demands systems.\r\n \r\n Product Specifications :\r\n \r\n \r\n \tFully synthesizable Register Transfer Level (RTL) Verilog HDL core\r\n \tTest Bench. (Environment Variable : Verilog)\r\n \tMethodologies based Test Bench UVM\r\n \tFault Simulation done\r\n \tTest Realization Portable Stimulus Standards (PSS)\r\n \tTargeted Synopsys® Zebu® EP 1\r\n \r\n \r\n Product Options :\r\n \r\n \r\n \tAdaptations :\r\n \t\r\n \t\t8 Bit 8051 Microcontroller Interface available.\r\n \t\t16 / 32 Standard possible.\r\n \t\tDMA Functionality possible.\r\n \t\r\n \t\r\n \tAdd ons Verification IP UVM VIP\r\n \r\n \tData 8 GT s (gigatransfers per second) which twice 2.0.\r\n \tLink width 16 lanes maximum 15.75 GB (gigabytes each direction.\r\n \tLane configuration has same lane as with lanes. Each can provide 985 MB bandwidth.\r\n \tIncreased flexibility also allowing be changed dynamically depending system.\r\n \tBackward compatibility backward compatible 1.0 meaning designed earlier versions slot but at speed.\r\n \tMulti function support multi functions through device reducing need expansion slots.\r\n \tPower than predecessors help reduce energy heat generation.\r\n """ "text_medium_priority" => "" "updated_at" => 1746218388 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ "matched_tokens" => array:1 [ …1] "snippet" => "SI23PCIe30 PCIe - PCI Express Controller Silicon Cores a Div. of Interfaces" ] "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ …1] "snippet" => "The PCIe 3.0 (Peripheral Component Interconnect" ] ] "highlights" => array:2 [ 0 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:1 [ …1] "snippet" => "The PCIe 3.0 (Peripheral Component Interconnect" ] 1 => array:3 [ "field" => "text_high_priority" "matched_tokens" => array:1 [ …1] "snippet" => "SI23PCIe30 PCIe - PCI Express Controller Silicon Cores a Div. of Interfaces" ] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 2 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ 0 => "TSMC" ] "asic.foundry_node" => array:1 [ 0 => "TSMC_50" ] "asic.foundry_node_process" => array:1 [ 0 => "TSMC_50_" ] "asic.node" => array:1 [ 0 => 50 ] "asic.node_foundry" => array:1 [ 0 => "50_TSMC" ] "blockdiagram" => "/upload/catalog/product/blockdiagram/19696/icon_10g-phy-for-pcie-3-0-tsmc-n5-x1-north-south-vertical-poly-orientation-673c734e3d7f8..webp" "category.id" => array:1 [ 0 => 501 ] "category.name" => array:1 [ 0 => "Multi-Protocol PHY IP" ] "category.slug" => [] "created_at" => 1732018526 "id" => "19696" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_c10pcie3phy_tsmc5ff_x1ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G PHY for PCIe 3.0, TSMC N5 X1, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-phy-for-pcie-3-0-tsmc-n5-x1-north-south-vertical-poly-orientation-ip" "sortable_id" => 19696 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 501 ] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_c10pcie3phy_tsmc5ff_x1ns 10G PHY for PCIe 3.0 TSMC N5 X1 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018526 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ "matched_tokens" => array:1 [ …1] "snippet" => "dwc_c10pcie3phy_tsmc5ff_x1ns 10G PHY for PCIe 3.0 TSMC N5 X1 North/South (vertical) poly orientation Synopsys Inc." ] "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ …1] "snippet" => "latency in battery-operated consumer mobile applications. multi-protocol small area" ] ] "highlights" => array:2 [ 0 => array:3 [ "field" => "text_high_priority" "matched_tokens" => array:1 [ …1] "snippet" => "dwc_c10pcie3phy_tsmc5ff_x1ns 10G PHY for PCIe 3.0 TSMC N5 X1 North/South (vertical) poly orientation Synopsys Inc." ] 1 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:1 [ …1] "snippet" => "latency in battery-operated consumer mobile applications. multi-protocol small area" ] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 3 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ 0 => "TSMC" ] "asic.foundry_node" => array:1 [ 0 => "TSMC_160" ] "asic.foundry_node_process" => array:1 [ 0 => "TSMC_160_" ] "asic.node" => array:1 [ 0 => 160 ] "asic.node_foundry" => array:1 [ 0 => "160_TSMC" ] "blockdiagram" => "/upload/catalog/product/blockdiagram/19690/icon_10g-phy-for-pcie-3-0-tsmc-16ffpll-x8-north-south-vertical-poly-orientation-673c734d1d9fd..webp" "category.id" => array:1 [ 0 => 501 ] "category.name" => array:1 [ 0 => "Multi-Protocol PHY IP" ] "category.slug" => [] "created_at" => 1732018525 "id" => "19690" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_c10pcie3phy_tsmc16ffpll_x8ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G PHY for PCIe 3.0, TSMC 16FFPLL x8, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-phy-for-pcie-3-0-tsmc-16ffpll-x8-north-south-vertical-poly-orientation-ip" "sortable_id" => 19690 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 501 ] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_c10pcie3phy_tsmc16ffpll_x8ns 10G PHY for PCIe 3.0 TSMC 16FFPLL x8 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018525 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ "matched_tokens" => array:1 [ …1] "snippet" => "dwc_c10pcie3phy_tsmc16ffpll_x8ns 10G PHY for PCIe 3.0 TSMC 16FFPLL x8 North/South (vertical) poly orientation Synopsys Inc." ] "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ …1] "snippet" => "latency in battery-operated consumer mobile applications. multi-protocol small area" ] ] "highlights" => array:2 [ 0 => array:3 [ "field" => "text_high_priority" "matched_tokens" => array:1 [ …1] "snippet" => "dwc_c10pcie3phy_tsmc16ffpll_x8ns 10G PHY for PCIe 3.0 TSMC 16FFPLL x8 North/South (vertical) poly orientation Synopsys Inc." ] 1 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:1 [ …1] "snippet" => "latency in battery-operated consumer mobile applications. multi-protocol small area" ] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 4 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ 0 => "TSMC" ] "asic.foundry_node" => array:1 [ 0 => "TSMC_160" ] "asic.foundry_node_process" => array:1 [ 0 => "TSMC_160_" ] "asic.node" => array:1 [ 0 => 160 ] "asic.node_foundry" => array:1 [ 0 => "160_TSMC" ] "blockdiagram" => "/upload/catalog/product/blockdiagram/19689/icon_10g-phy-for-pcie-3-0-tsmc-16ffpll-x4-north-south-vertical-poly-orientation-673c734cda17a..webp" "category.id" => array:1 [ 0 => 501 ] "category.name" => array:1 [ 0 => "Multi-Protocol PHY IP" ] "category.slug" => [] "created_at" => 1732018524 "id" => "19689" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_c10pcie3phy_tsmc16ffpll_x4ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G PHY for PCIe 3.0, TSMC 16FFPLL x4, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-phy-for-pcie-3-0-tsmc-16ffpll-x4-north-south-vertical-poly-orientation-ip" "sortable_id" => 19689 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 501 ] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_c10pcie3phy_tsmc16ffpll_x4ns 10G PHY for PCIe 3.0 TSMC 16FFPLL x4 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018524 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ "matched_tokens" => array:1 [ …1] "snippet" => "dwc_c10pcie3phy_tsmc16ffpll_x4ns 10G PHY for PCIe 3.0 TSMC 16FFPLL x4 North/South (vertical) poly orientation Synopsys Inc." ] "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ …1] "snippet" => "latency in battery-operated consumer mobile applications. multi-protocol small area" ] ] "highlights" => array:2 [ 0 => array:3 [ "field" => "text_high_priority" "matched_tokens" => array:1 [ …1] "snippet" => "dwc_c10pcie3phy_tsmc16ffpll_x4ns 10G PHY for PCIe 3.0 TSMC 16FFPLL x4 North/South (vertical) poly orientation Synopsys Inc." ] 1 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:1 [ …1] "snippet" => "latency in battery-operated consumer mobile applications. multi-protocol small area" ] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 5 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ 0 => "TSMC" ] "asic.foundry_node" => array:1 [ 0 => "TSMC_120" ] "asic.foundry_node_process" => array:1 [ 0 => "TSMC_120_" ] "asic.node" => array:1 [ 0 => 120 ] "asic.node_foundry" => array:1 [ 0 => "120_TSMC" ] "blockdiagram" => "/upload/catalog/product/blockdiagram/19677/icon_10g-mp-phy-for-pcie-3-0-usxgmii-sgmii-tsmc-12ffc-x1-north-south-vertical-poly-orientation-673c7349f1490..webp" "category.id" => array:1 [ 0 => 501 ] "category.name" => array:1 [ 0 => "Multi-Protocol PHY IP" ] "category.slug" => [] "created_at" => 1732018521 "id" => "19677" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_mp10usxgmiiphy_tsmc12ffcx1ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G MP PHY for PCIe 3.0/USXGMII/SGMII, TSMC 12FFC x1, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-mp-phy-for-pcie-3-0-usxgmii-sgmii-tsmc-12ffc-x1-north-south-vertical-poly-orientation-ip" "sortable_id" => 19677 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 501 ] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_mp10usxgmiiphy_tsmc12ffcx1ns 10G MP PHY for PCIe 3.0/USXGMII/SGMII TSMC 12FFC x1 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018522 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ "matched_tokens" => array:1 [ …1] "snippet" => "dwc_mp10usxgmiiphy_tsmc12ffcx1ns 10G MP PHY for PCIe 3.0/USXGMII/SGMII TSMC 12FFC x1 North/South (vertical) poly orientation Synopsys Inc." ] "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ …1] "snippet" => "latency in battery-operated consumer mobile applications. multi-protocol small area" ] ] "highlights" => array:2 [ 0 => array:3 [ "field" => "text_high_priority" "matched_tokens" => array:1 [ …1] "snippet" => "dwc_mp10usxgmiiphy_tsmc12ffcx1ns 10G MP PHY for PCIe 3.0/USXGMII/SGMII TSMC 12FFC x1 North/South (vertical) poly orientation Synopsys Inc." ] 1 => array:3 [ "field" => "text_low_priority" "matched_tokens" => array:1 [ …1] "snippet" => "latency in battery-operated consumer mobile applications. multi-protocol small area" ] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 6 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ 0 => "Samsung" ] "asic.foundry_node" => array:1 [ 0 => "Samsung_50" ] "asic.foundry_node_process" => array:1 [ 0 => "Samsung_50_" ] "asic.node" => array:1 [ 0 => 50 ] "asic.node_foundry" => array:1 [ 0 => "50_Samsung" ] "blockdiagram" => "/upload/catalog/product/blockdiagram/19675/icon_10g-phy-for-pcie-3-0-ss-sf5-x2-north-south-vertical-poly-orientation-673c73498f73a..webp" "category.id" => array:1 [ 0 => 501 ] "category.name" => array:1 [ 0 => "Multi-Protocol PHY IP" ] "category.slug" => [] "created_at" => 1732018521 "id" => "19675" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_c10pcie3phy_ss5lpex2ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ 0 => "sip" ] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G PHY for PCIe 3.0, SS SF5 x2, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-phy-for-pcie-3-0-ss-sf5-x2-north-south-vertical-poly-orientation-ip" "sortable_id" => 19675 "taxo0" => array:1 [ 0 => 1 ] "taxo1" => array:1 [ 0 => 7 ] "taxo2" => array:1 [ 0 => 501 ] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_c10pcie3phy_ss5lpex2ns 10G PHY for PCIe 3.0 SS SF5 x2 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018521 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ "matched_tokens" => array:1 [ …1] "snippet" => "dwc_c10pcie3phy_ss5lpex2ns 10G PHY for PCIe 3.0 SS SF5 x2 North/South (vertical) poly orientation Synopsys Inc." ] "text_low_priority" => array:2 [ "matched_tokens" => array:1 [ …1] "snippet" => "latency in battery-operated consumer mobile applications. multi-protocol small area" ] ] "highlights" => array:2 [ 0 => array:3 [ "field" => "text_high_priority" "matched_tokens" => array:1 [ …1] "snippet" => "dwc_c10pcie3phy_ss5lpex2ns 10G PHY for PCIe 3.0 SS SF5 x2 North/South (vertical) poly orientation Synopsys Inc." ] 1 => array:3 [ "field" => "text_low_priority" …2 ] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 7 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/19674/icon_10g-phy-for-pcie-3-0-ss-sf5-x1-north-south-vertical-poly-orientation-673c7349622bf..webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1732018521 "id" => "19674" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_c10pcie3phy_ss5lpex1ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G PHY for PCIe 3.0, SS SF5 x1, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-phy-for-pcie-3-0-ss-sf5-x1-north-south-vertical-poly-orientation-ip" "sortable_id" => 19674 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_c10pcie3phy_ss5lpex1ns 10G PHY for PCIe 3.0 SS SF5 x1 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018521 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 8 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/18075/icon_pcie-3-diagram-67af36b5600d4.png.webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1723569094 "id" => "18075" "keyfeatures" => """ <ul>\r\n \t<li>Supports PCIe 3.1, USB 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSMII/SGMII</li>\r\n \t<li>Multi-protocol support for simultaneous independent links</li>\r\n \t<li>Supports SRIS and internal SSC generation</li>\r\n \t<li>Supports PCIe L1 sub-states</li>\r\n \t<li>Automatic calibration of on-chip termination resistors</li>\r\n \t<li>Supports internal and external clock sources with clock active detection</li>\r\n \t<li>SCAN, BIST, and serial/parallel loopback functions</li>\r\n </ul> """ "keyfeatures_cn" => "" "keywords" => "" "logo" => "tality-66bb475ed438e.webp" "logo2" => "tality-66bb475ed438e.webp" "name" => "asic.node" "overview" => "The IP for 10Gbps Multi-Protocol PHY IP is a lower active and low leakage power design crafted for mobile, IoT, consumer, and automotive designs. The PHY IP is designed for multi-protocols running on a single PHY macro and is compliant with USB 3.1, PCI Express® (PCIe®) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, 10G-KR and QSGMII/SGMII specifications. The PCS complies with the PIPE 4.x interfaces and supports dynamic equalization features of different protocols. \u{200B}" "overview_cn" => "" "partnumber" => "PHY for PCIe 3.1" "priority" => 15 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 24 "provider.name" => "Cadence Design Systems, Inc." "provider.object" => "{"id":24,"name":"Cadence Design Systems, Inc.","providerslug":"cadence-design-systems-inc"}" "provider.priority" => 1501 "provider.slug" => "cadence-design-systems-inc" "published_as_new_at" => 0 "seofeatures" => """ <ul>\r\n \t<li>Supports PCIe 3.1, USB 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSMII/SGMII</li>\r\n \t<li>Multi-protocol support for simultaneous independent links</li>\r\n \t<li>Supports SRIS and internal SSC generation</li>\r\n \t<li>Supports PCIe L1 sub-states</li>\r\n \t<li>Automatic calibration of on-chip termination resistors</li>\r\n \t<li>Supports internal and external clock sources with clock active detection</li>\r\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "PHY for PCIe 3.1" "shortdescription_cn" => "" "slug" => "pcie-4-3-2-serdes-phy-globalfoundries-12nm" "sortable_id" => 18075 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => array:1 [ …1] "taxo4" => array:1 [ …1] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "PHY for PCIe 3.1 Cadence Design Systems Inc." "text_low_priority" => """ The IP for 10Gbps Multi-Protocol PHY is a lower active and low leakage power design crafted mobile IoT consumer automotive designs. designed multi-protocols running on single macro compliant with USB 3.1 PCI Express® (PCIe®) DisplayPort TX v1.4 Embedded v1.4b SATA 3 10G-KR QSGMII/SGMII specifications. PCS complies the PIPE 4.x interfaces supports dynamic equalization features of different protocols. \u{200B} \r\n \tSupports PCIe DP-TX v1.4/eDP-TX QSMII/SGMII\r\n \tMulti-protocol support simultaneous independent links\r\n \tSupports SRIS internal SSC generation\r\n \tSupports L1 sub-states\r\n \tAutomatic calibration on-chip termination resistors\r\n \tSupports external clock sources detection\r\n \tSCAN BIST serial/parallel loopback functions\r\n """ "text_medium_priority" => "" "updated_at" => 1739491200 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 9 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "/upload/catalog/product/blockdiagram/14256/icon_usb-3-0-pcie-2-0-combo-phy-ip-silicon-proven-in-tsmc-28hpc-66bb7645bef87.PNG.webp" "category.id" => array:3 [ …3] "category.name" => array:3 [ …3] "category.slug" => [] "created_at" => 1607695538 "id" => "14256" "keyfeatures" => "<ul><li>Standard PHY interface (PIPE) enables multiple IP sources for PCIe/USB3 MAC layer</li><li>Supports 2.5GT/s and 5.0GT/s serial data transmission rate</li><li>Supports 16-bit or 32-bit parallel interface</li><li>Data and clock recovery from serial stream</li><li>8b/10b encoder/decoder and error indication</li><li>Support direct disparity control for use in transmitting compliance pattern in Pole mode</li><li>Support power change and rate change at a same PCLK edge in PCIe mode</li><li>Tunable Receiver detection to detect worse case cables</li><li>Beacon transmission and reception in Pole mode</li><li>Low Frequency Periodic Signaling (LFPS) transmission and reception in USB 3.0 mode</li><li>Support SSCG function to reduce EMI effects with tunable down spread amplitude</li><li>Selectable TX margining, Tx de-emphasis and signal swing values</li><li>Internal Loopback Test Capable</li><li>Allowable analog circuit parameter adjustment and internal test control</li><li>Compliant with USB3/PCIe base specification</li><li>Silicon Proven in TSMC 28HPC+.</li></ul>" "keyfeatures_cn" => "<ul><li>标准PHY接口（PIPE）可为PCIe/USB3 MAC层提供多个IP源\r</li><li>支持2.5GT/s和5.0GT/s的串行数据传输速率\r</li><li>支持16位或32位并行接口\r</li><li>从串行流中获得的数据和时钟恢复\r</li><li>8b/10b编码器/解码器和错误指示\r</li><li>支持直接视差控制，用于在极点模式下的传输遵从性模式\r</li><li>支持在PCIe模式下在同一PCLK边缘的功率变化和速率变化\r</li><li>可调接收器检测检测更坏的情况电缆\r</li><li>在极点模式下的信标传输和接收\r</li><li>USB 3.0模式下的低频周期信号（LFPS）传输和接收\r</li><li>支持SSCG功能，通过可调谐的向下扩展幅度来降低EMI效应\r</li><li>可选择的TX边缘，TX去重和信号摆动值\r</li><li>内部回撤测试能力\r</li><li>允许的模拟电路参数调整和内部试验控制\r</li><li>符合USB3/PCIe基本规范\r</li><li>在TSMC 28HPC+工艺上通过硅验证</li></ul>" "keywords" => "USB 3.0combo PHY, SATA 3.0, PCIe2.0, combo serdes, combo phy ip, usb combo phy in tsmc,USB3.2, usb 3.2 phy, usb 3.2 in umc, usb 3.2 in 28nm,USB 3.1 phy, usb3Gen1PHY, USB 3.1 Gen2PHY,usb in smic,sata3.2, pcie3.1, usb comb phy, usb pcie sata combo,serdesip" "logo" => "t2m-v2-66bb477f994ef.webp" "logo2" => "t2m-v2-66bb477f994ef.webp" "name" => "asic.node" "overview" => "The Combo PHY is a complete USB 3.0 and PCIe 2.0 PHY IP solution designed for a mobile and data consumer applications in TSMC 28nm process. It supports both USB3.0 (1 or 2 ports) and PCIe 2.0 (1 lane). It consists of Physical Coding Sublayer and Physical Media Attachment and includes all circuitry for interface operation with 8/10 encoding/decoding, driver, input buffers, PLL and impedance matching circuitry. The PHY provides standard PIPE interface with the Media Access Layer for exchanging information. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption." "overview_cn" => "这个Combo PHYIP是完整的USB 3.0和PCIe 2.0 PHY IP解决方案，专为TSMC 28nm过程中的移动和数据消费者应用而设计。这个IP同时支持USB3.0 (1个或2个端口）和PCIe 2.0 (1个通道），由物理编码子层和物理媒体附件组成，包括所有用于8/10编码/解码、驱动器、输入缓冲器、PLL和阻抗匹配电路。这个PHY IP提供了具有媒体访问层的标准管道接口，用于交换信息。这个PHY IP通过额外的PLL控制、参考时钟控制和嵌入式电源门控控制，实现了低功耗。此外，上述低功率模式设置是可配置的，这个PHY IP广泛适用于在不同的功耗考虑下的各种场景." "partnumber" => "USB 3.0/ PCIe 2.0 Combo PHY IP in 28HPC+" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 206 "provider.name" => "T2M GmbH" "provider.object" => "{"id":206,"name":"T2M GmbH","providerslug":"t2m-gmbh"}" "provider.priority" => 2001 "provider.slug" => "t2m-gmbh" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Standard PHY interface (PIPE) enables multiple IP sources for PCIe/USB3 MAC layer</li>\n <li>Supports 2.5GT/s and 5.0GT/s serial data transmission rate</li>\n <li>Supports 16-bit or 32-bit parallel interface</li>\n <li>Data and clock recovery from serial stream</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+" "shortdescription_cn" => "USB 3.0/ PCIe 2.0 Combo PHY IP，在 TSMC 28HPC+ 中经过硅验证" "slug" => "usb-3-0-pcie-2-0-combo-phy-ip-silicon-proven-in-tsmc-28hpc" "sortable_id" => 14256 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:2 [ …2] "taxo3" => array:3 [ …3] "taxo4" => array:3 [ …3] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "USB 3.0/ PCIe 2.0 Combo PHY IP in 28HPC+ Silicon Proven TSMC T2M GmbH" "text_low_priority" => "The Combo PHY is a complete USB 3.0 and PCIe 2.0 IP solution designed for mobile data consumer applications in TSMC 28nm process. It supports both USB3.0 (1 or 2 ports) lane). consists of Physical Coding Sublayer Media Attachment includes all circuitry interface operation with 8/10 encoding/decoding driver input buffers PLL impedance matching circuitry. provides standard PIPE the Access Layer exchanging information. Lower power consumption achieved due to support additional control reference clock embedded gating control. Also since aforementioned low mode setting configurable widely applicable various scenarios under different consideration consumption. Standard (PIPE) enables multiple sources PCIe/USB3 MAC layerSupports 2.5GT/s 5.0GT/s serial transmission rateSupports 16-bit 32-bit parallel interfaceData recovery from stream8b/10b encoder/decoder error indicationSupport direct disparity use transmitting compliance pattern Pole modeSupport change rate at same PCLK edge modeTunable Receiver detection detect worse case cablesBeacon reception modeLow Frequency Periodic Signaling (LFPS) SSCG function reduce EMI effects tunable down spread amplitudeSelectable TX margining Tx de-emphasis signal swing valuesInternal Loopback Test CapableAllowable analog circuit parameter adjustment internal test controlCompliant USB3/PCIe base specificationSilicon Proven 28HPC+." "text_medium_priority" => "USB 3.0combo PHY SATA 3.0 PCIe2.0 combo serdes phy ip usb in tsmc USB3.2 3.2 umc 28nm 3.1 usb3Gen1PHY Gen2PHY smic sata3.2 pcie3.1 comb pcie sata serdesip" "updated_at" => 1681207255 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] ] "out_of" => 18250 "page" => 1 "request_params" => array:4 [ "collection_name" => "product_semiiphub" "first_q" => "Mobile PCIe" "per_page" => 10 "q" => "Mobile PCIe" ] "search_cutoff" => false "search_time_ms" => 5 ] 1 => array:8 [ "facet_counts" => array:6 [ 0 => array:4 [ "counts" => array:12 [ 0 => array:3 [ …3] 1 => array:3 [ …3] 2 => array:3 [ …3] 3 => array:3 [ …3] 4 => array:3 [ …3] 5 => array:3 [ …3] 6 => array:3 [ …3] 7 => array:3 [ …3] 8 => array:3 [ …3] 9 => array:3 [ …3] 10 => array:3 [ …3] 11 => array:3 [ …3] ] "field_name" => "provider.object" "sampled" => false "stats" => array:1 [ "total_values" => 12 ] ] 1 => array:4 [ "counts" => array:4 [ 0 => array:3 [ …3] 1 => array:3 [ …3] 2 => array:3 [ …3] 3 => array:3 [ …3] ] "field_name" => "asic.foundry" "sampled" => false "stats" => array:1 [ "total_values" => 4 ] ] 2 => array:4 [ "counts" => array:9 [ 0 => array:3 [ …3] 1 => array:3 [ …3] 2 => array:3 [ …3] 3 => array:3 [ …3] 4 => array:3 [ …3] 5 => array:3 [ …3] 6 => array:3 [ …3] 7 => array:3 [ …3] 8 => array:3 [ …3] ] "field_name" => "asic.foundry_node" "sampled" => false "stats" => array:1 [ "total_values" => 9 ] ] 3 => array:4 [ "counts" => array:9 [ 0 => array:3 [ …3] 1 => array:3 [ …3] 2 => array:3 [ …3] 3 => array:3 [ …3] 4 => array:3 [ …3] 5 => array:3 [ …3] 6 => array:3 [ …3] 7 => array:3 [ …3] 8 => array:3 [ …3] ] "field_name" => "asic.node_foundry" "sampled" => false "stats" => array:1 [ "total_values" => 9 ] ] 4 => array:4 [ "counts" => array:7 [ 0 => array:3 [ …3] 1 => array:3 [ …3] 2 => array:3 [ …3] 3 => array:3 [ …3] 4 => array:3 [ …3] 5 => array:3 [ …3] 6 => array:3 [ …3] ] "field_name" => "asic.node" "sampled" => false "stats" => array:5 [ "avg" => 136.875 "max" => 280.0 "min" => 50.0 "sum" => 2190.0 "total_values" => 7 ] ] 5 => array:4 [ "counts" => array:1 [ 0 => array:3 [ …3] ] "field_name" => "productTypes" "sampled" => false "stats" => array:1 [ "total_values" => 1 ] ] ] "found" => 40 "hits" => array:10 [ 0 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1757945168 "id" => "23759" "keyfeatures" => """ Compliant with the following specifications:\r\n \r\n <ul>\r\n \t<li>AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0</li>\r\n \t<li>AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0</li>\r\n \t<li>AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0</li>\r\n \t<li>AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0</li>\r\n </ul>\r\n \r\n DTI PCIe Controller supports:\r\n \r\n <ul>\r\n \t<li>Master only operation</li>\r\n \t<li>Slave only operation</li>\r\n \t<li>Master and slave operation</li>\r\n \t<li>Clock synchronization</li>\r\n \t<li>Programmable FIFO watermarks</li>\r\n \t<li>Interrupt interface</li>\r\n </ul> """ "keyfeatures_cn" => "" "keywords" => "" "logo" => "dolphinic-66bb47735e1d5.webp" "logo2" => "dolphinic-66bb47735e1d5.webp" "name" => "asic.node" "overview" => """ Dolphin PCIe Controller is a high-performance and compact solution for PCIe provide high-throughput, low-latency, and power-efficient external connectivity in SoCs for mobile, networking, storage, cloud computing, and automotive applications. \r\n \r\n The PCIe Controller consists of silicon-proven digital controllers, PHYs and verification IP, all of which are designed to support all required features of the PCIe 5.0 32GT/s (Gen5), PCIe 4.0 16GT/s (Gen4), 3.1 8GT/s (Gen3), 2.1 5GT/s (Gen2) and 1.1 2.5GT/s (Gen1). """ "overview_cn" => "" "partnumber" => "PCIe Controller" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ …1] "provider.id" => 139 "provider.name" => "Dolphin Technology" "provider.object" => "{"id":139,"name":"Dolphin Technology","providerslug":"dolphin-technology"}" "provider.priority" => 221 "provider.slug" => "dolphin-technology" "published_as_new_at" => 0 "seofeatures" => """ <ul>\r\n \t<li>Dolphin PCIe Controller is a high-performance and compact solution for PCIe provide high-throughput, low-latency, and power-efficient external connectivity in SoCs for mobile, networking, storage, cloud computing, and automotive applications.</li>\r\n \t<li>The PCIe Controller consists of silicon-proven digital controllers, PHYs and verification IP, all of which are designed to support all required features of the PCIe 5.0 32GT/s (Gen5), PCIe 4.0 16GT/s (Gen4), 3.1 8GT/s (Gen3), 2.1 5GT/s (Gen2) and 1.1 2.5GT/s (Gen1).</li>\r\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "PCIe Controller" "shortdescription_cn" => "" "slug" => "pcie-controller-ip-2" "sortable_id" => 23759 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => array:1 [ …1] "taxo4" => array:1 [ …1] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "PCIe Controller Dolphin Technology" "text_low_priority" => """ Dolphin PCIe Controller is a high-performance and compact solution for provide high-throughput low-latency power-efficient external connectivity in SoCs mobile networking storage cloud computing automotive applications.\r\n \r\n The consists of silicon-proven digital controllers PHYs verification IP all which are designed to support required features the 5.0 32GT/s (Gen5) 4.0 16GT/s (Gen4) 3.1 8GT/s (Gen3) 2.1 5GT/s (Gen2) 1.1 2.5GT/s (Gen1). Compliant with following specifications:\r\n \r\n \r\n \tAMBA Advanced Peripheral Bus (APB) Specification Version 2.0\r\n \tAMBA High-performance (AHB) eXtensibale (AXI) 4.0\r\n \tAMBA Lite (AXI-Lite) 4.0\r\n \r\n \r\n DTI supports:\r\n \r\n \r\n \tMaster only operation\r\n \tSlave operation\r\n \tMaster slave operation\r\n \tClock synchronization\r\n \tProgrammable FIFO watermarks\r\n \tInterrupt interface\r\n """ "text_medium_priority" => "" "updated_at" => 1757946996 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 1 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "/upload/catalog/product/blockdiagram/22769/icon_2025-05-02-203723-68151173f201d.png.webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1746218387 "id" => "22769" "keyfeatures" => """ <ul>\r\n \t<li>Data transfer rate : PCIe 3.0 supports a data transfer rate of up - to 8 GT / s (gigatransfers per second), which is twice the speed of 2.0.</li>\r\n \t<li>Link width : The link width for PCIe 3.0 is up to 16 lanes, which provides a maximum bandwidth of 15.75 GB / s (gigabytes per second) in each direction.</li>\r\n \t<li>Lane configuration : PCIe 3.0 has the same lane configuration as its predecessor, PCIe 2.0, with up to 16 lanes. Each lane can provide up to 985 MB / s of bandwidth.</li>\r\n \t<li>Increased lane flexibility : PCIe 3.0 also offers increased lane flexibility, allowing the configuration of lanes to be changed dynamically depending on the needs of the system.</li>\r\n \t<li>Backward compatibility : PCIe 3.0 is backward compatible with PCIe 2.0 and PCIe 1.0, meaning that devices designed for earlier PCIe versions can be used with a PCIe 3.0 slot, but at a reduced speed.</li>\r\n \t<li>Multi - function support : PCIe 3.0 supports multi - function devices, which can provide multiple functions through a single physical device, reducing the need for multiple expansion slots.</li>\r\n \t<li>Power consumption : PCIe 3.0 is designed to be more power - efficient than its predecessors, which can help to reduce energy consumption and heat generation.</li>\r\n </ul> """ "keyfeatures_cn" => "" "keywords" => "" "logo" => "siliconcores-66bb476255681.webp" "logo2" => "siliconcores-66bb476255681.webp" "name" => "asic.node" "overview" => """ The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect various components to a computer's motherboard. It is the third generation of the PCIe standard and offers increased bandwidth, improved performance, and reduced power consumption compared to its predecessor, PCIe 2.0 Overall, PCIe 3.0 provides faster and more efficient communication between the various components in a computer, including graphics cards, network adapters, and storage devices, resulting in better overall performance.\r\n \r\n PCIe 3.0 is a high - speed, bidirectional, and low - cost point-to-point interface that is widely used in PC, consumer electronics, and mobile architectures. It supports dynamic attachment of multiple peripherals to the host via a switch or a bridge. PCIe 3.0 is an open architecture that offers higher data throughput and enables the connection of up to 128 devices to a single port on the motherboard. It is a serial protocol and physical link that transmits data differentially on multiple pairs of wires, while simultaneously providing power to the connected peripherals.\r\n \r\n As technology advances, new types of devices, media formats, and storage systems require more bus bandwidth to deliver the desired user experience. In addition, user applications demand faster and more efficient connections between the PC and these increasingly sophisticated peripherals. PCIe 3.0 addresses these requirements by delivering a significantly higher transfer rate that matches the needs of modern usage scenarios and devices. Its increased bandwidth and other features make it an ideal interface standard for meeting the performance demands of modern computer systems.\r\n \r\n Product Specifications :\r\n \r\n <ul>\r\n \t<li>Fully synthesizable Register Transfer Level (RTL) Verilog HDL core</li>\r\n \t<li>Test Bench. (Environment Variable : Verilog)</li>\r\n \t<li>Methodologies - based Test Bench : UVM</li>\r\n \t<li>Fault Simulation done</li>\r\n \t<li>Test Realization in Portable Stimulus Standards (PSS)</li>\r\n \t<li>Targeted to Synopsys® Zebu® EP - 1</li>\r\n </ul>\r\n \r\n Product Options :\r\n \r\n <ul>\r\n \t<li>Adaptations :\r\n \t<ul>\r\n \t\t<li>8 Bit 8051 Microcontroller Interface available.</li>\r\n \t\t<li>16 / 32 Bit Standard Microcontroller Interface possible.</li>\r\n \t\t<li>DMA Functionality possible.</li>\r\n \t</ul>\r\n \t</li>\r\n \t<li>Add - ons : Verification IP - UVM VIP</li>\r\n </ul> """ "overview_cn" => "" "partnumber" => "SI23PCIe30" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 44 "provider.name" => "Silicon Cores - a Div. of Silicon Interfaces" "provider.object" => "{"id":44,"name":"Silicon Cores - a Div. of Silicon Interfaces","providerslug":"silicon-cores-a-div-of-silicon-interfaces"}" "provider.priority" => 1 "provider.slug" => "silicon-cores-a-div-of-silicon-interfaces" "published_as_new_at" => 0 "seofeatures" => """ <ul>\r\n \t<li>The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect various components to a computer's motherboard.</li>\r\n \t<li>It is the third generation of the PCIe standard and offers increased bandwidth, improved performance, and reduced power consumption compared to its predecessor, PCIe 2.0 Overall, PCIe 3.0 provides faster and more efficient communication between the various components in a computer, including graphics cards, network adapters, and storage devices, resulting in better overall performance.</li>\r\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "PCIe - PCI Express Controller" "shortdescription_cn" => "" "slug" => "pcie-pci-express-controller-ip" "sortable_id" => 22769 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => array:1 [ …1] "taxo4" => array:1 [ …1] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "SI23PCIe30 PCIe - PCI Express Controller Silicon Cores a Div. of Interfaces" "text_low_priority" => """ The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that used to connect various components computer's motherboard. It the third generation of and offers increased bandwidth improved performance reduced power consumption compared its predecessor 2.0 Overall provides faster more efficient communication between in including graphics cards network adapters storage devices resulting better overall performance.\r\n \r\n PCIe high - speed bidirectional low cost point-to-point widely PC consumer electronics mobile architectures. supports dynamic attachment multiple peripherals host via switch or bridge. an open architecture higher data throughput enables connection up 128 single port on serial protocol physical link transmits differentially pairs wires while simultaneously providing connected peripherals.\r\n \r\n As technology advances new types media formats systems require bus deliver desired user experience. In addition applications demand connections these increasingly sophisticated peripherals. addresses requirements by delivering significantly transfer rate matches needs modern usage scenarios devices. Its other features make it ideal for meeting demands systems.\r\n \r\n Product Specifications :\r\n \r\n \r\n \tFully synthesizable Register Transfer Level (RTL) Verilog HDL core\r\n \tTest Bench. (Environment Variable : Verilog)\r\n \tMethodologies based Test Bench UVM\r\n \tFault Simulation done\r\n \tTest Realization Portable Stimulus Standards (PSS)\r\n \tTargeted Synopsys® Zebu® EP 1\r\n \r\n \r\n Product Options :\r\n \r\n \r\n \tAdaptations :\r\n \t\r\n \t\t8 Bit 8051 Microcontroller Interface available.\r\n \t\t16 / 32 Standard possible.\r\n \t\tDMA Functionality possible.\r\n \t\r\n \t\r\n \tAdd ons Verification IP UVM VIP\r\n \r\n \tData 8 GT s (gigatransfers per second) which twice 2.0.\r\n \tLink width 16 lanes maximum 15.75 GB (gigabytes each direction.\r\n \tLane configuration has same lane as with lanes. Each can provide 985 MB bandwidth.\r\n \tIncreased flexibility also allowing be changed dynamically depending system.\r\n \tBackward compatibility backward compatible 1.0 meaning designed earlier versions slot but at speed.\r\n \tMulti function support multi functions through device reducing need expansion slots.\r\n \tPower than predecessors help reduce energy heat generation.\r\n """ "text_medium_priority" => "" "updated_at" => 1746218388 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 2 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/19696/icon_10g-phy-for-pcie-3-0-tsmc-n5-x1-north-south-vertical-poly-orientation-673c734e3d7f8..webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1732018526 "id" => "19696" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_c10pcie3phy_tsmc5ff_x1ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G PHY for PCIe 3.0, TSMC N5 X1, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-phy-for-pcie-3-0-tsmc-n5-x1-north-south-vertical-poly-orientation-ip" "sortable_id" => 19696 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_c10pcie3phy_tsmc5ff_x1ns 10G PHY for PCIe 3.0 TSMC N5 X1 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018526 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 3 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/19690/icon_10g-phy-for-pcie-3-0-tsmc-16ffpll-x8-north-south-vertical-poly-orientation-673c734d1d9fd..webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1732018525 "id" => "19690" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_c10pcie3phy_tsmc16ffpll_x8ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G PHY for PCIe 3.0, TSMC 16FFPLL x8, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-phy-for-pcie-3-0-tsmc-16ffpll-x8-north-south-vertical-poly-orientation-ip" "sortable_id" => 19690 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_c10pcie3phy_tsmc16ffpll_x8ns 10G PHY for PCIe 3.0 TSMC 16FFPLL x8 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018525 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 4 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/19689/icon_10g-phy-for-pcie-3-0-tsmc-16ffpll-x4-north-south-vertical-poly-orientation-673c734cda17a..webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1732018524 "id" => "19689" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_c10pcie3phy_tsmc16ffpll_x4ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G PHY for PCIe 3.0, TSMC 16FFPLL x4, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-phy-for-pcie-3-0-tsmc-16ffpll-x4-north-south-vertical-poly-orientation-ip" "sortable_id" => 19689 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_c10pcie3phy_tsmc16ffpll_x4ns 10G PHY for PCIe 3.0 TSMC 16FFPLL x4 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018524 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 5 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/19677/icon_10g-mp-phy-for-pcie-3-0-usxgmii-sgmii-tsmc-12ffc-x1-north-south-vertical-poly-orientation-673c7349f1490..webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1732018521 "id" => "19677" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_mp10usxgmiiphy_tsmc12ffcx1ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G MP PHY for PCIe 3.0/USXGMII/SGMII, TSMC 12FFC x1, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-mp-phy-for-pcie-3-0-usxgmii-sgmii-tsmc-12ffc-x1-north-south-vertical-poly-orientation-ip" "sortable_id" => 19677 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_mp10usxgmiiphy_tsmc12ffcx1ns 10G MP PHY for PCIe 3.0/USXGMII/SGMII TSMC 12FFC x1 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018522 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 6 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/19675/icon_10g-phy-for-pcie-3-0-ss-sf5-x2-north-south-vertical-poly-orientation-673c73498f73a..webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1732018521 "id" => "19675" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_c10pcie3phy_ss5lpex2ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G PHY for PCIe 3.0, SS SF5 x2, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-phy-for-pcie-3-0-ss-sf5-x2-north-south-vertical-poly-orientation-ip" "sortable_id" => 19675 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_c10pcie3phy_ss5lpex2ns 10G PHY for PCIe 3.0 SS SF5 x2 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018521 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 7 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/19674/icon_10g-phy-for-pcie-3-0-ss-sf5-x1-north-south-vertical-poly-orientation-673c7349622bf..webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1732018521 "id" => "19674" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_c10pcie3phy_ss5lpex1ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G PHY for PCIe 3.0, SS SF5 x1, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-phy-for-pcie-3-0-ss-sf5-x1-north-south-vertical-poly-orientation-ip" "sortable_id" => 19674 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_c10pcie3phy_ss5lpex1ns 10G PHY for PCIe 3.0 SS SF5 x1 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018521 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 8 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/18075/icon_pcie-3-diagram-67af36b5600d4.png.webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1723569094 "id" => "18075" "keyfeatures" => """ <ul>\r\n \t<li>Supports PCIe 3.1, USB 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSMII/SGMII</li>\r\n \t<li>Multi-protocol support for simultaneous independent links</li>\r\n \t<li>Supports SRIS and internal SSC generation</li>\r\n \t<li>Supports PCIe L1 sub-states</li>\r\n \t<li>Automatic calibration of on-chip termination resistors</li>\r\n \t<li>Supports internal and external clock sources with clock active detection</li>\r\n \t<li>SCAN, BIST, and serial/parallel loopback functions</li>\r\n </ul> """ "keyfeatures_cn" => "" "keywords" => "" "logo" => "tality-66bb475ed438e.webp" "logo2" => "tality-66bb475ed438e.webp" "name" => "asic.node" "overview" => "The IP for 10Gbps Multi-Protocol PHY IP is a lower active and low leakage power design crafted for mobile, IoT, consumer, and automotive designs. The PHY IP is designed for multi-protocols running on a single PHY macro and is compliant with USB 3.1, PCI Express® (PCIe®) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, 10G-KR and QSGMII/SGMII specifications. The PCS complies with the PIPE 4.x interfaces and supports dynamic equalization features of different protocols. \u{200B}" "overview_cn" => "" "partnumber" => "PHY for PCIe 3.1" "priority" => 15 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 24 "provider.name" => "Cadence Design Systems, Inc." "provider.object" => "{"id":24,"name":"Cadence Design Systems, Inc.","providerslug":"cadence-design-systems-inc"}" "provider.priority" => 1501 "provider.slug" => "cadence-design-systems-inc" "published_as_new_at" => 0 "seofeatures" => """ <ul>\r\n \t<li>Supports PCIe 3.1, USB 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSMII/SGMII</li>\r\n \t<li>Multi-protocol support for simultaneous independent links</li>\r\n \t<li>Supports SRIS and internal SSC generation</li>\r\n \t<li>Supports PCIe L1 sub-states</li>\r\n \t<li>Automatic calibration of on-chip termination resistors</li>\r\n \t<li>Supports internal and external clock sources with clock active detection</li>\r\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "PHY for PCIe 3.1" "shortdescription_cn" => "" "slug" => "pcie-4-3-2-serdes-phy-globalfoundries-12nm" "sortable_id" => 18075 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => array:1 [ …1] "taxo4" => array:1 [ …1] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "PHY for PCIe 3.1 Cadence Design Systems Inc." "text_low_priority" => """ The IP for 10Gbps Multi-Protocol PHY is a lower active and low leakage power design crafted mobile IoT consumer automotive designs. designed multi-protocols running on single macro compliant with USB 3.1 PCI Express® (PCIe®) DisplayPort TX v1.4 Embedded v1.4b SATA 3 10G-KR QSGMII/SGMII specifications. PCS complies the PIPE 4.x interfaces supports dynamic equalization features of different protocols. \u{200B} \r\n \tSupports PCIe DP-TX v1.4/eDP-TX QSMII/SGMII\r\n \tMulti-protocol support simultaneous independent links\r\n \tSupports SRIS internal SSC generation\r\n \tSupports L1 sub-states\r\n \tAutomatic calibration on-chip termination resistors\r\n \tSupports external clock sources detection\r\n \tSCAN BIST serial/parallel loopback functions\r\n """ "text_medium_priority" => "" "updated_at" => 1739491200 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 9 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "/upload/catalog/product/blockdiagram/14256/icon_usb-3-0-pcie-2-0-combo-phy-ip-silicon-proven-in-tsmc-28hpc-66bb7645bef87.PNG.webp" "category.id" => array:3 [ …3] "category.name" => array:3 [ …3] "category.slug" => [] "created_at" => 1607695538 "id" => "14256" "keyfeatures" => "<ul><li>Standard PHY interface (PIPE) enables multiple IP sources for PCIe/USB3 MAC layer</li><li>Supports 2.5GT/s and 5.0GT/s serial data transmission rate</li><li>Supports 16-bit or 32-bit parallel interface</li><li>Data and clock recovery from serial stream</li><li>8b/10b encoder/decoder and error indication</li><li>Support direct disparity control for use in transmitting compliance pattern in Pole mode</li><li>Support power change and rate change at a same PCLK edge in PCIe mode</li><li>Tunable Receiver detection to detect worse case cables</li><li>Beacon transmission and reception in Pole mode</li><li>Low Frequency Periodic Signaling (LFPS) transmission and reception in USB 3.0 mode</li><li>Support SSCG function to reduce EMI effects with tunable down spread amplitude</li><li>Selectable TX margining, Tx de-emphasis and signal swing values</li><li>Internal Loopback Test Capable</li><li>Allowable analog circuit parameter adjustment and internal test control</li><li>Compliant with USB3/PCIe base specification</li><li>Silicon Proven in TSMC 28HPC+.</li></ul>" "keyfeatures_cn" => "<ul><li>标准PHY接口（PIPE）可为PCIe/USB3 MAC层提供多个IP源\r</li><li>支持2.5GT/s和5.0GT/s的串行数据传输速率\r</li><li>支持16位或32位并行接口\r</li><li>从串行流中获得的数据和时钟恢复\r</li><li>8b/10b编码器/解码器和错误指示\r</li><li>支持直接视差控制，用于在极点模式下的传输遵从性模式\r</li><li>支持在PCIe模式下在同一PCLK边缘的功率变化和速率变化\r</li><li>可调接收器检测检测更坏的情况电缆\r</li><li>在极点模式下的信标传输和接收\r</li><li>USB 3.0模式下的低频周期信号（LFPS）传输和接收\r</li><li>支持SSCG功能，通过可调谐的向下扩展幅度来降低EMI效应\r</li><li>可选择的TX边缘，TX去重和信号摆动值\r</li><li>内部回撤测试能力\r</li><li>允许的模拟电路参数调整和内部试验控制\r</li><li>符合USB3/PCIe基本规范\r</li><li>在TSMC 28HPC+工艺上通过硅验证</li></ul>" "keywords" => "USB 3.0combo PHY, SATA 3.0, PCIe2.0, combo serdes, combo phy ip, usb combo phy in tsmc,USB3.2, usb 3.2 phy, usb 3.2 in umc, usb 3.2 in 28nm,USB 3.1 phy, usb3Gen1PHY, USB 3.1 Gen2PHY,usb in smic,sata3.2, pcie3.1, usb comb phy, usb pcie sata combo,serdesip" "logo" => "t2m-v2-66bb477f994ef.webp" "logo2" => "t2m-v2-66bb477f994ef.webp" "name" => "asic.node" "overview" => "The Combo PHY is a complete USB 3.0 and PCIe 2.0 PHY IP solution designed for a mobile and data consumer applications in TSMC 28nm process. It supports both USB3.0 (1 or 2 ports) and PCIe 2.0 (1 lane). It consists of Physical Coding Sublayer and Physical Media Attachment and includes all circuitry for interface operation with 8/10 encoding/decoding, driver, input buffers, PLL and impedance matching circuitry. The PHY provides standard PIPE interface with the Media Access Layer for exchanging information. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption." "overview_cn" => "这个Combo PHYIP是完整的USB 3.0和PCIe 2.0 PHY IP解决方案，专为TSMC 28nm过程中的移动和数据消费者应用而设计。这个IP同时支持USB3.0 (1个或2个端口）和PCIe 2.0 (1个通道），由物理编码子层和物理媒体附件组成，包括所有用于8/10编码/解码、驱动器、输入缓冲器、PLL和阻抗匹配电路。这个PHY IP提供了具有媒体访问层的标准管道接口，用于交换信息。这个PHY IP通过额外的PLL控制、参考时钟控制和嵌入式电源门控控制，实现了低功耗。此外，上述低功率模式设置是可配置的，这个PHY IP广泛适用于在不同的功耗考虑下的各种场景." "partnumber" => "USB 3.0/ PCIe 2.0 Combo PHY IP in 28HPC+" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 206 "provider.name" => "T2M GmbH" "provider.object" => "{"id":206,"name":"T2M GmbH","providerslug":"t2m-gmbh"}" "provider.priority" => 2001 "provider.slug" => "t2m-gmbh" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Standard PHY interface (PIPE) enables multiple IP sources for PCIe/USB3 MAC layer</li>\n <li>Supports 2.5GT/s and 5.0GT/s serial data transmission rate</li>\n <li>Supports 16-bit or 32-bit parallel interface</li>\n <li>Data and clock recovery from serial stream</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+" "shortdescription_cn" => "USB 3.0/ PCIe 2.0 Combo PHY IP，在 TSMC 28HPC+ 中经过硅验证" "slug" => "usb-3-0-pcie-2-0-combo-phy-ip-silicon-proven-in-tsmc-28hpc" "sortable_id" => 14256 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:2 [ …2] "taxo3" => array:3 [ …3] "taxo4" => array:3 [ …3] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "USB 3.0/ PCIe 2.0 Combo PHY IP in 28HPC+ Silicon Proven TSMC T2M GmbH" "text_low_priority" => "The Combo PHY is a complete USB 3.0 and PCIe 2.0 IP solution designed for mobile data consumer applications in TSMC 28nm process. It supports both USB3.0 (1 or 2 ports) lane). consists of Physical Coding Sublayer Media Attachment includes all circuitry interface operation with 8/10 encoding/decoding driver input buffers PLL impedance matching circuitry. provides standard PIPE the Access Layer exchanging information. Lower power consumption achieved due to support additional control reference clock embedded gating control. Also since aforementioned low mode setting configurable widely applicable various scenarios under different consideration consumption. Standard (PIPE) enables multiple sources PCIe/USB3 MAC layerSupports 2.5GT/s 5.0GT/s serial transmission rateSupports 16-bit 32-bit parallel interfaceData recovery from stream8b/10b encoder/decoder error indicationSupport direct disparity use transmitting compliance pattern Pole modeSupport change rate at same PCLK edge modeTunable Receiver detection detect worse case cablesBeacon reception modeLow Frequency Periodic Signaling (LFPS) SSCG function reduce EMI effects tunable down spread amplitudeSelectable TX margining Tx de-emphasis signal swing valuesInternal Loopback Test CapableAllowable analog circuit parameter adjustment internal test controlCompliant USB3/PCIe base specificationSilicon Proven 28HPC+." "text_medium_priority" => "USB 3.0combo PHY SATA 3.0 PCIe2.0 combo serdes phy ip usb in tsmc USB3.2 3.2 umc 28nm 3.1 usb3Gen1PHY Gen2PHY smic sata3.2 pcie3.1 comb pcie sata serdesip" "updated_at" => 1681207255 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] ] "out_of" => 18250 "page" => 1 "request_params" => array:4 [ "collection_name" => "product_semiiphub" "first_q" => "Mobile PCIe" "per_page" => 10 "q" => "Mobile PCIe" ] "search_cutoff" => false "search_time_ms" => 7 ] 2 => array:8 [ "facet_counts" => array:6 [ 0 => array:4 [ "counts" => array:12 [ 0 => array:3 [ …3] 1 => array:3 [ …3] 2 => array:3 [ …3] 3 => array:3 [ …3] 4 => array:3 [ …3] 5 => array:3 [ …3] 6 => array:3 [ …3] 7 => array:3 [ …3] 8 => array:3 [ …3] 9 => array:3 [ …3] 10 => array:3 [ …3] 11 => array:3 [ …3] ] "field_name" => "provider.object" "sampled" => false "stats" => array:1 [ "total_values" => 12 ] ] 1 => array:4 [ "counts" => array:4 [ 0 => array:3 [ …3] 1 => array:3 [ …3] 2 => array:3 [ …3] 3 => array:3 [ …3] ] "field_name" => "asic.foundry" "sampled" => false "stats" => array:1 [ "total_values" => 4 ] ] 2 => array:4 [ "counts" => array:9 [ 0 => array:3 [ …3] 1 => array:3 [ …3] 2 => array:3 [ …3] 3 => array:3 [ …3] 4 => array:3 [ …3] 5 => array:3 [ …3] 6 => array:3 [ …3] 7 => array:3 [ …3] 8 => array:3 [ …3] ] "field_name" => "asic.foundry_node" "sampled" => false "stats" => array:1 [ "total_values" => 9 ] ] 3 => array:4 [ "counts" => array:9 [ 0 => array:3 [ …3] 1 => array:3 [ …3] 2 => array:3 [ …3] 3 => array:3 [ …3] 4 => array:3 [ …3] 5 => array:3 [ …3] 6 => array:3 [ …3] 7 => array:3 [ …3] 8 => array:3 [ …3] ] "field_name" => "asic.node_foundry" "sampled" => false "stats" => array:1 [ "total_values" => 9 ] ] 4 => array:4 [ "counts" => array:7 [ 0 => array:3 [ …3] 1 => array:3 [ …3] 2 => array:3 [ …3] 3 => array:3 [ …3] 4 => array:3 [ …3] 5 => array:3 [ …3] 6 => array:3 [ …3] ] "field_name" => "asic.node" "sampled" => false "stats" => array:5 [ "avg" => 136.875 "max" => 280.0 "min" => 50.0 "sum" => 2190.0 "total_values" => 7 ] ] 5 => array:4 [ "counts" => array:1 [ 0 => array:3 [ …3] ] "field_name" => "productTypes" "sampled" => false "stats" => array:1 [ "total_values" => 1 ] ] ] "found" => 40 "hits" => array:10 [ 0 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1757945168 "id" => "23759" "keyfeatures" => """ Compliant with the following specifications:\r\n \r\n <ul>\r\n \t<li>AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0</li>\r\n \t<li>AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0</li>\r\n \t<li>AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0</li>\r\n \t<li>AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0</li>\r\n </ul>\r\n \r\n DTI PCIe Controller supports:\r\n \r\n <ul>\r\n \t<li>Master only operation</li>\r\n \t<li>Slave only operation</li>\r\n \t<li>Master and slave operation</li>\r\n \t<li>Clock synchronization</li>\r\n \t<li>Programmable FIFO watermarks</li>\r\n \t<li>Interrupt interface</li>\r\n </ul> """ "keyfeatures_cn" => "" "keywords" => "" "logo" => "dolphinic-66bb47735e1d5.webp" "logo2" => "dolphinic-66bb47735e1d5.webp" "name" => "asic.node" "overview" => """ Dolphin PCIe Controller is a high-performance and compact solution for PCIe provide high-throughput, low-latency, and power-efficient external connectivity in SoCs for mobile, networking, storage, cloud computing, and automotive applications. \r\n \r\n The PCIe Controller consists of silicon-proven digital controllers, PHYs and verification IP, all of which are designed to support all required features of the PCIe 5.0 32GT/s (Gen5), PCIe 4.0 16GT/s (Gen4), 3.1 8GT/s (Gen3), 2.1 5GT/s (Gen2) and 1.1 2.5GT/s (Gen1). """ "overview_cn" => "" "partnumber" => "PCIe Controller" "priority" => 1 "priority_taxo" => 0 "productTypes" => array:1 [ …1] "provider.id" => 139 "provider.name" => "Dolphin Technology" "provider.object" => "{"id":139,"name":"Dolphin Technology","providerslug":"dolphin-technology"}" "provider.priority" => 221 "provider.slug" => "dolphin-technology" "published_as_new_at" => 0 "seofeatures" => """ <ul>\r\n \t<li>Dolphin PCIe Controller is a high-performance and compact solution for PCIe provide high-throughput, low-latency, and power-efficient external connectivity in SoCs for mobile, networking, storage, cloud computing, and automotive applications.</li>\r\n \t<li>The PCIe Controller consists of silicon-proven digital controllers, PHYs and verification IP, all of which are designed to support all required features of the PCIe 5.0 32GT/s (Gen5), PCIe 4.0 16GT/s (Gen4), 3.1 8GT/s (Gen3), 2.1 5GT/s (Gen2) and 1.1 2.5GT/s (Gen1).</li>\r\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "PCIe Controller" "shortdescription_cn" => "" "slug" => "pcie-controller-ip-2" "sortable_id" => 23759 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => array:1 [ …1] "taxo4" => array:1 [ …1] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "PCIe Controller Dolphin Technology" "text_low_priority" => """ Dolphin PCIe Controller is a high-performance and compact solution for provide high-throughput low-latency power-efficient external connectivity in SoCs mobile networking storage cloud computing automotive applications.\r\n \r\n The consists of silicon-proven digital controllers PHYs verification IP all which are designed to support required features the 5.0 32GT/s (Gen5) 4.0 16GT/s (Gen4) 3.1 8GT/s (Gen3) 2.1 5GT/s (Gen2) 1.1 2.5GT/s (Gen1). Compliant with following specifications:\r\n \r\n \r\n \tAMBA Advanced Peripheral Bus (APB) Specification Version 2.0\r\n \tAMBA High-performance (AHB) eXtensibale (AXI) 4.0\r\n \tAMBA Lite (AXI-Lite) 4.0\r\n \r\n \r\n DTI supports:\r\n \r\n \r\n \tMaster only operation\r\n \tSlave operation\r\n \tMaster slave operation\r\n \tClock synchronization\r\n \tProgrammable FIFO watermarks\r\n \tInterrupt interface\r\n """ "text_medium_priority" => "" "updated_at" => 1757946996 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 1 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "/upload/catalog/product/blockdiagram/22769/icon_2025-05-02-203723-68151173f201d.png.webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1746218387 "id" => "22769" "keyfeatures" => """ <ul>\r\n \t<li>Data transfer rate : PCIe 3.0 supports a data transfer rate of up - to 8 GT / s (gigatransfers per second), which is twice the speed of 2.0.</li>\r\n \t<li>Link width : The link width for PCIe 3.0 is up to 16 lanes, which provides a maximum bandwidth of 15.75 GB / s (gigabytes per second) in each direction.</li>\r\n \t<li>Lane configuration : PCIe 3.0 has the same lane configuration as its predecessor, PCIe 2.0, with up to 16 lanes. Each lane can provide up to 985 MB / s of bandwidth.</li>\r\n \t<li>Increased lane flexibility : PCIe 3.0 also offers increased lane flexibility, allowing the configuration of lanes to be changed dynamically depending on the needs of the system.</li>\r\n \t<li>Backward compatibility : PCIe 3.0 is backward compatible with PCIe 2.0 and PCIe 1.0, meaning that devices designed for earlier PCIe versions can be used with a PCIe 3.0 slot, but at a reduced speed.</li>\r\n \t<li>Multi - function support : PCIe 3.0 supports multi - function devices, which can provide multiple functions through a single physical device, reducing the need for multiple expansion slots.</li>\r\n \t<li>Power consumption : PCIe 3.0 is designed to be more power - efficient than its predecessors, which can help to reduce energy consumption and heat generation.</li>\r\n </ul> """ "keyfeatures_cn" => "" "keywords" => "" "logo" => "siliconcores-66bb476255681.webp" "logo2" => "siliconcores-66bb476255681.webp" "name" => "asic.node" "overview" => """ The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect various components to a computer's motherboard. It is the third generation of the PCIe standard and offers increased bandwidth, improved performance, and reduced power consumption compared to its predecessor, PCIe 2.0 Overall, PCIe 3.0 provides faster and more efficient communication between the various components in a computer, including graphics cards, network adapters, and storage devices, resulting in better overall performance.\r\n \r\n PCIe 3.0 is a high - speed, bidirectional, and low - cost point-to-point interface that is widely used in PC, consumer electronics, and mobile architectures. It supports dynamic attachment of multiple peripherals to the host via a switch or a bridge. PCIe 3.0 is an open architecture that offers higher data throughput and enables the connection of up to 128 devices to a single port on the motherboard. It is a serial protocol and physical link that transmits data differentially on multiple pairs of wires, while simultaneously providing power to the connected peripherals.\r\n \r\n As technology advances, new types of devices, media formats, and storage systems require more bus bandwidth to deliver the desired user experience. In addition, user applications demand faster and more efficient connections between the PC and these increasingly sophisticated peripherals. PCIe 3.0 addresses these requirements by delivering a significantly higher transfer rate that matches the needs of modern usage scenarios and devices. Its increased bandwidth and other features make it an ideal interface standard for meeting the performance demands of modern computer systems.\r\n \r\n Product Specifications :\r\n \r\n <ul>\r\n \t<li>Fully synthesizable Register Transfer Level (RTL) Verilog HDL core</li>\r\n \t<li>Test Bench. (Environment Variable : Verilog)</li>\r\n \t<li>Methodologies - based Test Bench : UVM</li>\r\n \t<li>Fault Simulation done</li>\r\n \t<li>Test Realization in Portable Stimulus Standards (PSS)</li>\r\n \t<li>Targeted to Synopsys® Zebu® EP - 1</li>\r\n </ul>\r\n \r\n Product Options :\r\n \r\n <ul>\r\n \t<li>Adaptations :\r\n \t<ul>\r\n \t\t<li>8 Bit 8051 Microcontroller Interface available.</li>\r\n \t\t<li>16 / 32 Bit Standard Microcontroller Interface possible.</li>\r\n \t\t<li>DMA Functionality possible.</li>\r\n \t</ul>\r\n \t</li>\r\n \t<li>Add - ons : Verification IP - UVM VIP</li>\r\n </ul> """ "overview_cn" => "" "partnumber" => "SI23PCIe30" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 44 "provider.name" => "Silicon Cores - a Div. of Silicon Interfaces" "provider.object" => "{"id":44,"name":"Silicon Cores - a Div. of Silicon Interfaces","providerslug":"silicon-cores-a-div-of-silicon-interfaces"}" "provider.priority" => 1 "provider.slug" => "silicon-cores-a-div-of-silicon-interfaces" "published_as_new_at" => 0 "seofeatures" => """ <ul>\r\n \t<li>The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect various components to a computer's motherboard.</li>\r\n \t<li>It is the third generation of the PCIe standard and offers increased bandwidth, improved performance, and reduced power consumption compared to its predecessor, PCIe 2.0 Overall, PCIe 3.0 provides faster and more efficient communication between the various components in a computer, including graphics cards, network adapters, and storage devices, resulting in better overall performance.</li>\r\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "PCIe - PCI Express Controller" "shortdescription_cn" => "" "slug" => "pcie-pci-express-controller-ip" "sortable_id" => 22769 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => array:1 [ …1] "taxo4" => array:1 [ …1] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "SI23PCIe30 PCIe - PCI Express Controller Silicon Cores a Div. of Interfaces" "text_low_priority" => """ The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that used to connect various components computer's motherboard. It the third generation of and offers increased bandwidth improved performance reduced power consumption compared its predecessor 2.0 Overall provides faster more efficient communication between in including graphics cards network adapters storage devices resulting better overall performance.\r\n \r\n PCIe high - speed bidirectional low cost point-to-point widely PC consumer electronics mobile architectures. supports dynamic attachment multiple peripherals host via switch or bridge. an open architecture higher data throughput enables connection up 128 single port on serial protocol physical link transmits differentially pairs wires while simultaneously providing connected peripherals.\r\n \r\n As technology advances new types media formats systems require bus deliver desired user experience. In addition applications demand connections these increasingly sophisticated peripherals. addresses requirements by delivering significantly transfer rate matches needs modern usage scenarios devices. Its other features make it ideal for meeting demands systems.\r\n \r\n Product Specifications :\r\n \r\n \r\n \tFully synthesizable Register Transfer Level (RTL) Verilog HDL core\r\n \tTest Bench. (Environment Variable : Verilog)\r\n \tMethodologies based Test Bench UVM\r\n \tFault Simulation done\r\n \tTest Realization Portable Stimulus Standards (PSS)\r\n \tTargeted Synopsys® Zebu® EP 1\r\n \r\n \r\n Product Options :\r\n \r\n \r\n \tAdaptations :\r\n \t\r\n \t\t8 Bit 8051 Microcontroller Interface available.\r\n \t\t16 / 32 Standard possible.\r\n \t\tDMA Functionality possible.\r\n \t\r\n \t\r\n \tAdd ons Verification IP UVM VIP\r\n \r\n \tData 8 GT s (gigatransfers per second) which twice 2.0.\r\n \tLink width 16 lanes maximum 15.75 GB (gigabytes each direction.\r\n \tLane configuration has same lane as with lanes. Each can provide 985 MB bandwidth.\r\n \tIncreased flexibility also allowing be changed dynamically depending system.\r\n \tBackward compatibility backward compatible 1.0 meaning designed earlier versions slot but at speed.\r\n \tMulti function support multi functions through device reducing need expansion slots.\r\n \tPower than predecessors help reduce energy heat generation.\r\n """ "text_medium_priority" => "" "updated_at" => 1746218388 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 2 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/19696/icon_10g-phy-for-pcie-3-0-tsmc-n5-x1-north-south-vertical-poly-orientation-673c734e3d7f8..webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1732018526 "id" => "19696" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_c10pcie3phy_tsmc5ff_x1ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G PHY for PCIe 3.0, TSMC N5 X1, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-phy-for-pcie-3-0-tsmc-n5-x1-north-south-vertical-poly-orientation-ip" "sortable_id" => 19696 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_c10pcie3phy_tsmc5ff_x1ns 10G PHY for PCIe 3.0 TSMC N5 X1 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018526 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 3 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/19690/icon_10g-phy-for-pcie-3-0-tsmc-16ffpll-x8-north-south-vertical-poly-orientation-673c734d1d9fd..webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1732018525 "id" => "19690" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_c10pcie3phy_tsmc16ffpll_x8ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G PHY for PCIe 3.0, TSMC 16FFPLL x8, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-phy-for-pcie-3-0-tsmc-16ffpll-x8-north-south-vertical-poly-orientation-ip" "sortable_id" => 19690 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_c10pcie3phy_tsmc16ffpll_x8ns 10G PHY for PCIe 3.0 TSMC 16FFPLL x8 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018525 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 4 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/19689/icon_10g-phy-for-pcie-3-0-tsmc-16ffpll-x4-north-south-vertical-poly-orientation-673c734cda17a..webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1732018524 "id" => "19689" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_c10pcie3phy_tsmc16ffpll_x4ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G PHY for PCIe 3.0, TSMC 16FFPLL x4, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-phy-for-pcie-3-0-tsmc-16ffpll-x4-north-south-vertical-poly-orientation-ip" "sortable_id" => 19689 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_c10pcie3phy_tsmc16ffpll_x4ns 10G PHY for PCIe 3.0 TSMC 16FFPLL x4 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018524 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 5 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/19677/icon_10g-mp-phy-for-pcie-3-0-usxgmii-sgmii-tsmc-12ffc-x1-north-south-vertical-poly-orientation-673c7349f1490..webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1732018521 "id" => "19677" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_mp10usxgmiiphy_tsmc12ffcx1ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G MP PHY for PCIe 3.0/USXGMII/SGMII, TSMC 12FFC x1, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-mp-phy-for-pcie-3-0-usxgmii-sgmii-tsmc-12ffc-x1-north-south-vertical-poly-orientation-ip" "sortable_id" => 19677 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_mp10usxgmiiphy_tsmc12ffcx1ns 10G MP PHY for PCIe 3.0/USXGMII/SGMII TSMC 12FFC x1 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018522 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 6 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/19675/icon_10g-phy-for-pcie-3-0-ss-sf5-x2-north-south-vertical-poly-orientation-673c73498f73a..webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1732018521 "id" => "19675" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_c10pcie3phy_ss5lpex2ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G PHY for PCIe 3.0, SS SF5 x2, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-phy-for-pcie-3-0-ss-sf5-x2-north-south-vertical-poly-orientation-ip" "sortable_id" => 19675 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_c10pcie3phy_ss5lpex2ns 10G PHY for PCIe 3.0 SS SF5 x2 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018521 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 7 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/19674/icon_10g-phy-for-pcie-3-0-ss-sf5-x1-north-south-vertical-poly-orientation-673c7349622bf..webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1732018521 "id" => "19674" "keyfeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li><li>Superior signal integrity across lossy backplanes enabled by a high-performance analog front-end that includes adaptive continuous time linear equalizer (CTLE), decision feedback equalization (DFE) and feed forward equalization (FFE)Low active and standby power consumption compared to competing solutions due to L1 sub-states, power gating and novel transmitter design</li><li>Spread Spectrum Clock (SSC)</li><li>Separate Reference Clock Independent SSC (SRIS)</li><li>Reference clock sharing for aggregated macro configurations</li><li>PCI Express Aggregation and bifurcation</li><li>Embedded bit error rate (BER) tester and internal eye monitor</li><li>Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker</li><li>Supports flip chip and wirebond packaging</li><li>Supports IEEE 1149.6 AC Boundary Scan</li><li>Supports -40C to 125C Tj</li></ul>" "keyfeatures_cn" => "" "keywords" => "Multi-Protocol 10G PHY" "logo" => "synopsys-66bb475c04b38.svg" "logo2" => "synopsys-66bb475c04b38.svg" "name" => "asic.node" "overview" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency in battery-operated consumer and mobile applications. The multi-protocol 10G PHY is small in area and provides low active and standby power while exceeding signal integrity and jitter performance of the PCI Express 3.1, SATA 6G and Ethernet standards.The transmitter and receiver equalizers enable customers to control and optimize signal integrity and at-speed performance. Continuous Calibration and Adaptation (CCA) provides a robust performance across voltage and temperature variations during normal mode of operation. The PHY incorporates advanced power saving features such as L1 sub-states in-conjunction with power gating in standby mode of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, with optional I/O supply under drive to further save active power.The PHY's Automatic Test Equipment (ATE) capabilities and optional wirebond packaging reduce the overall bill of materials (BOM) cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the Synopsys Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success. These features reduce both product development cycles and accelerates time-to-market." "overview_cn" => "" "partnumber" => "dwc_c10pcie3phy_ss5lpex1ns" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 5 "provider.name" => "Synopsys, Inc." "provider.object" => "{"id":5,"name":"Synopsys, Inc.","providerslug":"synopsys-inc"}" "provider.priority" => 12841 "provider.slug" => "synopsys-inc" "published_as_new_at" => 0 "seofeatures" => "<ul><li>Supports 1.25 Gbps to 10 Gbps data rates</li><li>Supports PCI Express 3.1, SATA 6G, SGMII</li><li>Supports x1 to x16 macro configurations</li></ul>" "seofeatures_cn" => "" "shortdescription" => "10G PHY for PCIe 3.0, SS SF5 x1, North/South (vertical) poly orientation" "shortdescription_cn" => "" "slug" => "10g-phy-for-pcie-3-0-ss-sf5-x1-north-south-vertical-poly-orientation-ip" "sortable_id" => 19674 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => [] "taxo4" => [] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "dwc_c10pcie3phy_ss5lpex1ns 10G PHY for PCIe 3.0 SS SF5 x1 North/South (vertical) poly orientation Synopsys Inc." "text_low_priority" => "The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio meeting the growing needs for low-power consumption and low latency in battery-operated consumer mobile applications. multi-protocol small area provides active standby power while exceeding signal integrity jitter performance PCI Express 3.1 SATA 6G Ethernet standards.The transmitter receiver equalizers enable customers to control optimize at-speed performance. Continuous Calibration Adaptation (CCA) robust across voltage temperature variations during normal mode operation. incorporates advanced saving features such as L1 sub-states in-conjunction with gating hybrid transmit drivers support high swing current optional I/O supply under drive further save power.The PHY's Automatic Test Equipment (ATE) capabilities wirebond packaging reduce overall bill materials (BOM) cost. embedded bit error rate (BER) tester internal eye monitor provide on-chip testability visibility into channel integrates seamlessly Synopsys Physical Sublayers digital controllers/media access controllers (MACs) design time help designers achieve first-pass silicon success. These both product development cycles accelerates time-to-market. Supports 1.25 Gbps 10 data ratesSupports SGMIISupports x1 x16 macro configurationsSuperior lossy backplanes enabled by analog front-end that includes adaptive continuous linear equalizer (CTLE) decision feedback equalization (DFE) feed forward (FFE)Low compared competing solutions due novel designSpread Spectrum Clock (SSC)Separate Reference Independent SSC (SRIS)Reference clock sharing aggregated configurationsPCI Aggregation bifurcationEmbedded monitorBuilt-in self test (BIST) including 7- 9- 11- 15- 16- 23- 31-bit pseudo random stream (PRBS) generation checkerSupports flip chip packagingSupports IEEE 1149.6 AC Boundary ScanSupports -40C 125C Tj" "text_medium_priority" => "Multi-Protocol 10G PHY " "updated_at" => 1732018521 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 8 => array:5 [ "document" => array:48 [ "asic.foundry" => array:1 [ …1] "asic.foundry_node" => array:1 [ …1] "asic.foundry_node_process" => array:1 [ …1] "asic.node" => array:1 [ …1] "asic.node_foundry" => array:1 [ …1] "blockdiagram" => "/upload/catalog/product/blockdiagram/18075/icon_pcie-3-diagram-67af36b5600d4.png.webp" "category.id" => array:1 [ …1] "category.name" => array:1 [ …1] "category.slug" => [] "created_at" => 1723569094 "id" => "18075" "keyfeatures" => """ <ul>\r\n \t<li>Supports PCIe 3.1, USB 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSMII/SGMII</li>\r\n \t<li>Multi-protocol support for simultaneous independent links</li>\r\n \t<li>Supports SRIS and internal SSC generation</li>\r\n \t<li>Supports PCIe L1 sub-states</li>\r\n \t<li>Automatic calibration of on-chip termination resistors</li>\r\n \t<li>Supports internal and external clock sources with clock active detection</li>\r\n \t<li>SCAN, BIST, and serial/parallel loopback functions</li>\r\n </ul> """ "keyfeatures_cn" => "" "keywords" => "" "logo" => "tality-66bb475ed438e.webp" "logo2" => "tality-66bb475ed438e.webp" "name" => "asic.node" "overview" => "The IP for 10Gbps Multi-Protocol PHY IP is a lower active and low leakage power design crafted for mobile, IoT, consumer, and automotive designs. The PHY IP is designed for multi-protocols running on a single PHY macro and is compliant with USB 3.1, PCI Express® (PCIe®) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, 10G-KR and QSGMII/SGMII specifications. The PCS complies with the PIPE 4.x interfaces and supports dynamic equalization features of different protocols. \u{200B}" "overview_cn" => "" "partnumber" => "PHY for PCIe 3.1" "priority" => 15 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 24 "provider.name" => "Cadence Design Systems, Inc." "provider.object" => "{"id":24,"name":"Cadence Design Systems, Inc.","providerslug":"cadence-design-systems-inc"}" "provider.priority" => 1501 "provider.slug" => "cadence-design-systems-inc" "published_as_new_at" => 0 "seofeatures" => """ <ul>\r\n \t<li>Supports PCIe 3.1, USB 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSMII/SGMII</li>\r\n \t<li>Multi-protocol support for simultaneous independent links</li>\r\n \t<li>Supports SRIS and internal SSC generation</li>\r\n \t<li>Supports PCIe L1 sub-states</li>\r\n \t<li>Automatic calibration of on-chip termination resistors</li>\r\n \t<li>Supports internal and external clock sources with clock active detection</li>\r\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "PHY for PCIe 3.1" "shortdescription_cn" => "" "slug" => "pcie-4-3-2-serdes-phy-globalfoundries-12nm" "sortable_id" => 18075 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:1 [ …1] "taxo3" => array:1 [ …1] "taxo4" => array:1 [ …1] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "PHY for PCIe 3.1 Cadence Design Systems Inc." "text_low_priority" => """ The IP for 10Gbps Multi-Protocol PHY is a lower active and low leakage power design crafted mobile IoT consumer automotive designs. designed multi-protocols running on single macro compliant with USB 3.1 PCI Express® (PCIe®) DisplayPort TX v1.4 Embedded v1.4b SATA 3 10G-KR QSGMII/SGMII specifications. PCS complies the PIPE 4.x interfaces supports dynamic equalization features of different protocols. \u{200B} \r\n \tSupports PCIe DP-TX v1.4/eDP-TX QSMII/SGMII\r\n \tMulti-protocol support simultaneous independent links\r\n \tSupports SRIS internal SSC generation\r\n \tSupports L1 sub-states\r\n \tAutomatic calibration on-chip termination resistors\r\n \tSupports external clock sources detection\r\n \tSCAN BIST serial/parallel loopback functions\r\n """ "text_medium_priority" => "" "updated_at" => 1739491200 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] 9 => array:5 [ "document" => array:48 [ "asic.foundry" => [] "asic.foundry_node" => [] "asic.foundry_node_process" => [] "asic.node" => [] "asic.node_foundry" => [] "blockdiagram" => "/upload/catalog/product/blockdiagram/14256/icon_usb-3-0-pcie-2-0-combo-phy-ip-silicon-proven-in-tsmc-28hpc-66bb7645bef87.PNG.webp" "category.id" => array:3 [ …3] "category.name" => array:3 [ …3] "category.slug" => [] "created_at" => 1607695538 "id" => "14256" "keyfeatures" => "<ul><li>Standard PHY interface (PIPE) enables multiple IP sources for PCIe/USB3 MAC layer</li><li>Supports 2.5GT/s and 5.0GT/s serial data transmission rate</li><li>Supports 16-bit or 32-bit parallel interface</li><li>Data and clock recovery from serial stream</li><li>8b/10b encoder/decoder and error indication</li><li>Support direct disparity control for use in transmitting compliance pattern in Pole mode</li><li>Support power change and rate change at a same PCLK edge in PCIe mode</li><li>Tunable Receiver detection to detect worse case cables</li><li>Beacon transmission and reception in Pole mode</li><li>Low Frequency Periodic Signaling (LFPS) transmission and reception in USB 3.0 mode</li><li>Support SSCG function to reduce EMI effects with tunable down spread amplitude</li><li>Selectable TX margining, Tx de-emphasis and signal swing values</li><li>Internal Loopback Test Capable</li><li>Allowable analog circuit parameter adjustment and internal test control</li><li>Compliant with USB3/PCIe base specification</li><li>Silicon Proven in TSMC 28HPC+.</li></ul>" "keyfeatures_cn" => "<ul><li>标准PHY接口（PIPE）可为PCIe/USB3 MAC层提供多个IP源\r</li><li>支持2.5GT/s和5.0GT/s的串行数据传输速率\r</li><li>支持16位或32位并行接口\r</li><li>从串行流中获得的数据和时钟恢复\r</li><li>8b/10b编码器/解码器和错误指示\r</li><li>支持直接视差控制，用于在极点模式下的传输遵从性模式\r</li><li>支持在PCIe模式下在同一PCLK边缘的功率变化和速率变化\r</li><li>可调接收器检测检测更坏的情况电缆\r</li><li>在极点模式下的信标传输和接收\r</li><li>USB 3.0模式下的低频周期信号（LFPS）传输和接收\r</li><li>支持SSCG功能，通过可调谐的向下扩展幅度来降低EMI效应\r</li><li>可选择的TX边缘，TX去重和信号摆动值\r</li><li>内部回撤测试能力\r</li><li>允许的模拟电路参数调整和内部试验控制\r</li><li>符合USB3/PCIe基本规范\r</li><li>在TSMC 28HPC+工艺上通过硅验证</li></ul>" "keywords" => "USB 3.0combo PHY, SATA 3.0, PCIe2.0, combo serdes, combo phy ip, usb combo phy in tsmc,USB3.2, usb 3.2 phy, usb 3.2 in umc, usb 3.2 in 28nm,USB 3.1 phy, usb3Gen1PHY, USB 3.1 Gen2PHY,usb in smic,sata3.2, pcie3.1, usb comb phy, usb pcie sata combo,serdesip" "logo" => "t2m-v2-66bb477f994ef.webp" "logo2" => "t2m-v2-66bb477f994ef.webp" "name" => "asic.node" "overview" => "The Combo PHY is a complete USB 3.0 and PCIe 2.0 PHY IP solution designed for a mobile and data consumer applications in TSMC 28nm process. It supports both USB3.0 (1 or 2 ports) and PCIe 2.0 (1 lane). It consists of Physical Coding Sublayer and Physical Media Attachment and includes all circuitry for interface operation with 8/10 encoding/decoding, driver, input buffers, PLL and impedance matching circuitry. The PHY provides standard PIPE interface with the Media Access Layer for exchanging information. Lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption." "overview_cn" => "这个Combo PHYIP是完整的USB 3.0和PCIe 2.0 PHY IP解决方案，专为TSMC 28nm过程中的移动和数据消费者应用而设计。这个IP同时支持USB3.0 (1个或2个端口）和PCIe 2.0 (1个通道），由物理编码子层和物理媒体附件组成，包括所有用于8/10编码/解码、驱动器、输入缓冲器、PLL和阻抗匹配电路。这个PHY IP提供了具有媒体访问层的标准管道接口，用于交换信息。这个PHY IP通过额外的PLL控制、参考时钟控制和嵌入式电源门控控制，实现了低功耗。此外，上述低功率模式设置是可配置的，这个PHY IP广泛适用于在不同的功耗考虑下的各种场景." "partnumber" => "USB 3.0/ PCIe 2.0 Combo PHY IP in 28HPC+" "priority" => 1 "priority_taxo" => 1 "productTypes" => array:1 [ …1] "provider.id" => 206 "provider.name" => "T2M GmbH" "provider.object" => "{"id":206,"name":"T2M GmbH","providerslug":"t2m-gmbh"}" "provider.priority" => 2001 "provider.slug" => "t2m-gmbh" "published_as_new_at" => 0 "seofeatures" => """ <ul><li>Standard PHY interface (PIPE) enables multiple IP sources for PCIe/USB3 MAC layer</li>\n <li>Supports 2.5GT/s and 5.0GT/s serial data transmission rate</li>\n <li>Supports 16-bit or 32-bit parallel interface</li>\n <li>Data and clock recovery from serial stream</li>\n </ul> """ "seofeatures_cn" => "" "shortdescription" => "USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+" "shortdescription_cn" => "USB 3.0/ PCIe 2.0 Combo PHY IP，在 TSMC 28HPC+ 中经过硅验证" "slug" => "usb-3-0-pcie-2-0-combo-phy-ip-silicon-proven-in-tsmc-28hpc" "sortable_id" => 14256 "taxo0" => array:1 [ …1] "taxo1" => array:1 [ …1] "taxo2" => array:2 [ …2] "taxo3" => array:3 [ …3] "taxo4" => array:3 [ …3] "taxo5" => [] "taxo6" => [] "taxo7" => [] "taxo8" => [] "text_high_priority" => "USB 3.0/ PCIe 2.0 Combo PHY IP in 28HPC+ Silicon Proven TSMC T2M GmbH" "text_low_priority" => "The Combo PHY is a complete USB 3.0 and PCIe 2.0 IP solution designed for mobile data consumer applications in TSMC 28nm process. It supports both USB3.0 (1 or 2 ports) lane). consists of Physical Coding Sublayer Media Attachment includes all circuitry interface operation with 8/10 encoding/decoding driver input buffers PLL impedance matching circuitry. provides standard PIPE the Access Layer exchanging information. Lower power consumption achieved due to support additional control reference clock embedded gating control. Also since aforementioned low mode setting configurable widely applicable various scenarios under different consideration consumption. Standard (PIPE) enables multiple sources PCIe/USB3 MAC layerSupports 2.5GT/s 5.0GT/s serial transmission rateSupports 16-bit 32-bit parallel interfaceData recovery from stream8b/10b encoder/decoder error indicationSupport direct disparity use transmitting compliance pattern Pole modeSupport change rate at same PCLK edge modeTunable Receiver detection detect worse case cablesBeacon reception modeLow Frequency Periodic Signaling (LFPS) SSCG function reduce EMI effects tunable down spread amplitudeSelectable TX margining Tx de-emphasis signal swing valuesInternal Loopback Test CapableAllowable analog circuit parameter adjustment internal test controlCompliant USB3/PCIe base specificationSilicon Proven 28HPC+." "text_medium_priority" => "USB 3.0combo PHY SATA 3.0 PCIe2.0 combo serdes phy ip usb in tsmc USB3.2 3.2 umc 28nm 3.1 usb3Gen1PHY Gen2PHY smic sata3.2 pcie3.1 comb pcie sata serdesip" "updated_at" => 1681207255 ] "highlight" => array:2 [ "text_high_priority" => array:2 [ …2] "text_low_priority" => array:2 [ …2] ] "highlights" => array:2 [ 0 => array:3 [ …3] 1 => array:3 [ …3] ] "text_match" => 1186707366542835714 "text_match_info" => array:7 [ "best_field_score" => "1108091338752" "best_field_weight" => 15 "fields_matched" => 2 "num_tokens_dropped" => 0 "score" => "1186707366542835714" "tokens_matched" => 2 "typo_prefix_score" => 0 ] ] ] "out_of" => 18250 "page" => 1 "request_params" => array:4 [ "collection_name" => "product_semiiphub" "first_q" => "Mobile PCIe" "per_page" => 10 "q" => "Mobile PCIe" ] "search_cutoff" => false "search_time_ms" => 7 ] ]]

Compare 40 IP from 12 vendors (1 - 10)

PCIe Controller
- Dolphin PCIe Controller is a high-performance and compact solution for PCIe provide high-throughput, low-latency, and power-efficient external connectivity in SoCs for mobile, networking, storage, cloud computing, and automotive applications.
- The PCIe Controller consists of silicon-proven digital controllers, PHYs and verification IP, all of which are designed to support all required features of the PCIe 5.0 32GT/s (Gen5), PCIe 4.0 16GT/s (Gen4), 3.1 8GT/s (Gen3), 2.1 5GT/s (Gen2) and 1.1 2.5GT/s (Gen1).
PCIe - PCI Express Controller
- The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect various components to a computer's motherboard.
- It is the third generation of the PCIe standard and offers increased bandwidth, improved performance, and reduced power consumption compared to its predecessor, PCIe 2.0 Overall, PCIe 3.0 provides faster and more efficient communication between the various components in a computer, including graphics cards, network adapters, and storage devices, resulting in better overall performance.
10G PHY for PCIe 3.0, TSMC N5 X1, North/South (vertical) poly orientation
- Supports 1.25 Gbps to 10 Gbps data rates
- Supports PCI Express 3.1, SATA 6G, SGMII
- Supports x1 to x16 macro configurations
10G PHY for PCIe 3.0, TSMC 16FFPLL x8, North/South (vertical) poly orientation
- Supports 1.25 Gbps to 10 Gbps data rates
- Supports PCI Express 3.1, SATA 6G, SGMII
- Supports x1 to x16 macro configurations
10G PHY for PCIe 3.0, TSMC 16FFPLL x4, North/South (vertical) poly orientation
- Supports 1.25 Gbps to 10 Gbps data rates
- Supports PCI Express 3.1, SATA 6G, SGMII
- Supports x1 to x16 macro configurations
10G MP PHY for PCIe 3.0/USXGMII/SGMII, TSMC 12FFC x1, North/South (vertical) poly orientation
- Supports 1.25 Gbps to 10 Gbps data rates
- Supports PCI Express 3.1, SATA 6G, SGMII
- Supports x1 to x16 macro configurations
10G PHY for PCIe 3.0, SS SF5 x2, North/South (vertical) poly orientation
- Supports 1.25 Gbps to 10 Gbps data rates
- Supports PCI Express 3.1, SATA 6G, SGMII
- Supports x1 to x16 macro configurations
10G PHY for PCIe 3.0, SS SF5 x1, North/South (vertical) poly orientation
- Supports 1.25 Gbps to 10 Gbps data rates
- Supports PCI Express 3.1, SATA 6G, SGMII
- Supports x1 to x16 macro configurations
PHY for PCIe 3.1
- Supports PCIe 3.1, USB 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSMII/SGMII
- Multi-protocol support for simultaneous independent links
- Supports SRIS and internal SSC generation
- Supports PCIe L1 sub-states
- Automatic calibration of on-chip termination resistors
- Supports internal and external clock sources with clock active detection
USB 3.0/ PCIe 2.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
- Standard PHY interface (PIPE) enables multiple IP sources for PCIe/USB3 MAC layer
- Supports 2.5GT/s and 5.0GT/s serial data transmission rate
- Supports 16-bit or 32-bit parallel interface
- Data and clock recovery from serial stream

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Mobile PCIe IP