The IP for 10Gbps Multi-Protocol PHY IP is a lower active and low leakage power design crafted for mobile, IoT, consumer, and automotive designs. The PHY IP is designed for multi-protocols running on a single PHY macro and is compliant with USB 3.1, PCI Express® (PCIe®) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, 10G-KR and QSGMII/SGMII specifications. The PCS complies with the PIPE 4.x interfaces and supports dynamic equalization features of different protocols.
PHY for PCIe 3.1
Overview
Key Features
- Supports PCIe 3.1, USB 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSMII/SGMII
- Multi-protocol support for simultaneous independent links
- Supports SRIS and internal SSC generation
- Supports PCIe L1 sub-states
- Automatic calibration of on-chip termination resistors
- Supports internal and external clock sources with clock active detection
- SCAN, BIST, and serial/parallel loopback functions
Benefits
- Multi-Protocol with Multi-Link Capability: Single-PHY macro offers optimum SoC configurability with the protocol mix and match
- Optimized Performance, Power, and Area: Best fit for the application's required performance with small footprint
- Comprehensive Test Feature Enables Rapid SoC Development: Extensive BIST and DFT enable ease of integration, faster bring-up, and quick debugging
Block Diagram
Deliverables
- PMA Hard Macro
- PCS-BIST Soft Macro
- Datasheet
- SoC integration guide
- Optional design integration and bring-up support services
Technical Specifications
Maturity
In Production
GLOBALFOUNDRIES
In Production:
12nm