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JESD204B IP

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Compare 108 IP from 17 vendors (1 - 10)
  • JESD204B
    • Standard version: JESD204B.01, January 2012
    • Versions Available: Transmitter / Receiver
    • Silicon Agnostic: Targets ASIC, ASSP, FPGA
    Block Diagram -- JESD204B
  • JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP
    • Widest feature set available in market.
    • Scrambling and de-scrambling Included.
    • High performance transport layer support.
    • Build in test functions
    Block Diagram -- JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP
  • JESD204B IP Core
    • Subsets of JEDEC Standard No. 204B(JESD204B.01) July 2011
    • Rx core performs lane alignment based on Subclass 0 and Subclass 1
    • Rx core performs frame alignment detection / monitoring and octet reconstruction
    • Rx core performs user-enabled descrambling
    Block Diagram -- JESD204B IP Core
  • JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 28HPC+
    • Multiple lanes transceiver with data rate from 1Gbps to 16Gbps: Transceiver version including both receiver and transmitter
    • Transmitter only version available
    • 40bit/32bit/20bit/16bit selectable parallel data bus Independent per-lane power down control
    • Programmable transmit amplitude
  • JESD204B /204C PHY&MAC
    • X4/X8 Lane Mode, support up to 25Gbps (per lane)
    • Shared common PLL based architecture
    • Digitally-control-impedance termination resistors and On-chip resistance calibration
    • Configurable TX output differential voltage swing
  • JESD204B Transmitter and Receiver
    • Applicable in RADAR, Medical Imaging as it supports higher bandwidth and more number of channels with fewer pins to simplify layout.
  • JESD204B PHY & Controller
    • Support for serial data rates up to 12.5Gbps
    • Supports Subclass 0, 1 and 2.
    • Supports 4 lanes.
    • Supports 1-32 converters.
  • JESD204B Controller
    • Supports for serial data rates up to 12.5Gbps
    • Supports Subclass 0, 1 and 2
    • Supports 1-24 lanes
    • Supports 1-32 converters
  • JESD204B RX IP
    •  X8 Lane Mode, up to 16Gbps per lane
    •  Serialization interface width
    • PHY- User interface support 16/20/32/40 bit
    •  Shared common PLL based architecture
  • JESD204B TX IP
    •  X4 Lane Mode, support 1.6875G to 16Gbps (per lane)
    •  Serialization interface width
    •  Shared common PLL based architecture
    •  Power Consumption
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