Vendor: SmartDV Technologies Category: JESD204

JESD204B Transmitter IIP

JESD204B interface provides full support for the JESD204B synchronous serial interface,compatible with JESD204B.01 version specif…

Contact Provider Request Datasheet

Overview

JESD204B interface provides full support for the JESD204B synchronous serial interface,compatible with JESD204B.01 version specification. Through its compatibility,it provides a simple interface to a wide range of low-cost devices. JESD204B Transmitter IIP is proven in FPGA environment. The host interface of the JESD204B can be simple interface or can be AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or Custom protocol.

JESD204B Transmitter IIP is supported natively in Verilog and VHDL

Key features

  • Compliant with JESD204 specification JESD204A, JESD204B.01.
  • Full JESD204B transmit functionality.
  • Supports data rate upto 12.5 Gbps.
  • Supports programmable clock frequency up to 12.5 GHz.
  • Supports up to Subclass 0, 1, 2.
  • Supports up to Version A and B.
  • Supports 1 to 8 lanes.
  • Supports 1 to 8 converters per transmitter.
  • Supports frame sizes of 1,2,4,8 and 16 octets per frame.
  • Supports HD-mode.
  • Supports 1 to 32 bit data width per converter.
  • Supports CF = 0 and 1 control words per frame clock period per link.
  • Supports 0 to 3 control bits per sample.
  • Supports 1 to 8 samples per converter.
  • Supports 1 to 32 frames per multiframe.
  • Supports 4, 8, 12, 16, 20, 24, 28 and 32 bits per sample.
  • Supports 0 to 15 bank ID – extension to DID.
  • Supports 0 to 255 device identification number.
  • Supports 0 to 7 lane identification number.
  • Supports different Serdes interfaces 10,20,40,60 bits and custom bits per lane.
  • Continuous sequence of a scrambled jitter pattern (JSPAT) and modified random pattern (modified RPAT).
  • Continuous sequence of either /D21.5/ or /K28.5/ characters for code group synchronization.
  • Repeated transmission of a lane alignment sequence, preceded by a code group synchronization sequence.
  • Scrambler can be enabled or disabled.
  • Supports 8b/10b encoding.
  • MCDA-ML (Multiple-Converter Device Alignment, Multiple-Lanes) device supported.

Block Diagram

JESD204B Transmitter IIP block diagram

Benefits

  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs,license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

What’s Included?

  • The JESD204B Transmitter interface is available in Source and netlist products.
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases.
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
  • IP-XACT RDL generated address map.
  • Firmware code and Linux driver package.
  • Documentation contains User's Guide and Release notes.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
JESD204B Transmitter IIP
Vendor
SmartDV Technologies

Provider

SmartDV Technologies
HQ: India
At SmartDV Technologies™, we believe there’s a better way to approach semiconductor intellectual property (IP) for integrated circuits. We’ve been focused exclusively on IP since 2007—so whether you’re sourcing standards-based design IP for your next SoC, ASIC, or FPGA, or seeking verification solutions (VIP) to put your chip design through its paces, you’ll find SmartDV’s IP straightforward to integrate. By combining proprietary SmartCompiler™ technology with the knowledge of hundreds of expert engineers, SmartDV can customize IP to meet your unique design objectives: quickly, economically, and reliably. Don’t allow other suppliers to force onesize-fits-all cores into your chip design. Get the IP you need, tailored to your specifications, with SmartDV: IP Your Way.
Contact SmartDV Technologies

Learn more about JESD204 IP core

JESD204 Frame Mapping explained from converter samples to lanes

The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Multiple ways JESD204 performs bitstream alignment

Bitstream alignment is a function of the Receiver (RX), as seen in the figure below it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes.

Frequently asked questions about JESD204 IP cores

What is JESD204B Transmitter IIP?

JESD204B Transmitter IIP is a JESD204 IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP