GUC IP
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60
IP
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TSMC CLN7FF HBM3 PHY
- IGAHBMX03A is a HBM3 (High Bandwidth Memory) PHY IP compliant to the JEDEC HBM3 DRAM Specification Rev 0.95.
- Built on TSMC 7nm process node, it supports data rate up to 7200 Mbps per data pin with DFI 1:4 clock frequency ratio (controller clock : WCK = 1:4).
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TSMC CLN7FF HBM2E PHY IP
- High Bandwidth Memory (HBM2E) DRAM PHY
- Supports HBM 3.2Gbps
- Supports DFI 1:2
- Supports only BL4
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TSMC CLN5FF HBM PHY IP
- High Bandwidth Memory (HBM) DRAM PHY
- Supports HBM 3.6Gbps
- Supports DFI 1:2
- Supports only BL4
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TSMC CLN6FF/7FF Die-to-Die Interface PHY
- 32 full-duplex lanes per slice
- 8 slices are included in analog hard macro
- Lane repair
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TSMC CLN16FFGL+ HBM PHY IP
- High Bandwidth Memory (HBM) DRAM PHY
- Supports HBM 2Gbps
- Supports DFI 1:2
- Supports only BL4
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TSMC 5nm UCIe-A 32G LP Die to Die Interface
- TSMC 5nm UCIe-A 32G LP Die to Die Interface