TSMC CLN16FFGL+ HBM PHY IP
Overview
This datasheet describes GUC’s HBM (High Bandwidth Memory) PHY IP, which can be integrated with HBM memory controller to provide HBM functionality. The HBM PHY IP shall be an independent IP and can be provided by GUC or other IP vendors.
Key Features
- High Bandwidth Memory (HBM) DRAM PHY
- Supports HBM 2Gbps
- Supports DFI 1:2
- Supports only BL4
- Supports AWORD/DWORD bus parity
- Supports programmable parity latency, PL = 0 and 2 , of DQ parity function
- Supports HBM data bus inversion (DBI) and write data mask (DM)
- Supports ECC mode
- Supports single bank refresh
- Complete HBM PHY delivered as a hard macro component (includes I/O, PLL, and DLL)
- Supports HBM PHY internal loopback BIST
- Supports HBM lookback test, includes MISR and LFSR mode
- Supports IEEE 1500 instruction
- Supports HBM lane repairs with redundant pin for row/column/data
Technical Specifications
Foundry, Node
TSMC 16nm CLN16FFGL+
Maturity
Silicon proven
TSMC
Silicon Proven:
16nm