This IGAD2DX01A test report shows the functional and characterization test result of GUC Die-to-Die Interface PHY IP for 8 Gbps operation. For IP detailed functional information, please refer to IP datasheet for IGAD2DX01A. This test chip adopts TSMC CLN6FF
? Process: TSMC 6 nm 0.75 V/1.8 V CMOS LOGIC FinFET Process or
TSMC 7 nm 0.75 V/1.8 V CMOS LOGIC FinFET Process
This test chip adopts TSMC 6 nm 0.75 V/1.8 V CMOS LOGIC FinFET Process
? Layer & Device: High R Resistance, ULVT
? Metal Scheme: 1P15M (1X_h_1Xa_v_1Ya_h_5Y_vhvhv_2Yy2Yx2R) or
1P13M (1X_h_1Xa_v_1Ya_h_5Y_vhvhv_2Yy2Z)
This test chip adopts 1P15M (1X_h_1Xa_v_1Ya_h_5Y_vhvhv_2Yy2Yx2R)
TSMC CLN6FF/7FF Die-to-Die Interface PHY
Overview
Key Features
- 32 full-duplex lanes per slice
- 8 slices are included in analog hard macro
- Lane repair
- Data bus inversion
- Parity check
- Built-in test pattern and checker
- EHOST : APB , I2C, and JTAG register interface
- Built-in PLL
- 0.25pJ/bit power consumption
- 1.8V analog supply voltage for PLL and 0.75V analog/digital supply voltage
- Independent power down mode for analog blocks
- Operating junction temperature: -40°C ~ 125°C
- Process : TSMC 6nm 0.75V/1.8V CMOS LOGIC FinFET Process or TSMC 7nm 0.75V/1.8V CMOS LOGIC FinFET Process
- Metal Scheme : 1P15M (1X_h_1Xa_v_1Ya_h_5Y_vhvhv_2Yy2Yx2R) or 1P13M (1X_h_1Xa_v_1Ya_h_5Y_vhvhv_2Yy2Z)
- Special layer and device type: High R Resistance, ULVT
- Analog hard macro size: 690 um x 3037.44 um (2.096mm2) for horizontal macro and 3037.074 um x 690 um (2.096mm2) for vertical macro (pre-shrink)
- Logic gate count: 1.5M
- Supports both horizontal and vertical GDS orientation
Technical Specifications
Foundry, Node
TSMC 6nm CLN6FF
Maturity
Silicon proven
TSMC
Silicon Proven:
6nm