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Data Flow Processor IP

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Compare 67 IP from 32 vendors (1 - 10)
  • NPU IP Core for Data Center
    • Origin Evolution™ for Data Center offers out-of-the-box compatibility with popular LLM and CNN networks. Attention-based processing optimization and advanced memory management ensure optimal AI performance across a variety of today’s standard and emerging neural networks. Featuring a hardware and software co-designed architecture, Origin Evolution for Data Center scales to 128 TFLOPS in a single core, with multi-core performance to PetaFLOPs.
    Block Diagram -- NPU IP Core for Data Center
  • Graphics Processor Overlay IP Core
    • Technology independent soft IP Core for FPGA, ASIC and SoC devices
    • Supplied as human-readable VHDL (or Verilog) source code
    Block Diagram -- Graphics Processor Overlay IP Core
  • 64-bit RISC-V Application Processor Core
    • 64-bit RISC-V core
    • Linux capable
    • In-order 7-stage pipeline
    Block Diagram -- 64-bit RISC-V Application Processor Core
  • Cyber Escort Unit IP provides real time detection of sero day attacks on processor
    • Hardware protection on processor
    • Compliant with all processor families
    • Escort step by step the program execution
    • Protection against Cyber attack (ROP, JOP, Buffer overrun, etc.) and Fault Injection attack targeting the code execution
    Block Diagram -- Cyber Escort Unit IP provides real time detection of sero day attacks on processor
  • Baseband processor
    • The Ceva-BX2 baseband processor IP handles both signal-processing and control workloads with up to 16 GMACs per second performance and high-level-language programming.
    • It supports a range of integer and floating-point data types for a wide range of baseband applications like 5G PHY control, and exploits a high degree of parallelism, but with remarkably compact code size.
    • Optimized high-speed interfaces expedite connection to other Ceva cores or to accelerators.
    Block Diagram -- Baseband processor
  • Near-threshold voltage and ultra-wide dynamic voltage and frequency scaling (UW-DVFS)
    • Elimination of static margins
    • Operation at Near-Threshold Voltage (Minimum Energy Point)
    • Minima UWDVFS covers all operating points, scaling accurately to the minimum voltage needed by the application.
  • Image Signal Processor (5MP, 2X Sensors) IP
    • Self-contained, no external memory needed
    • ARM® Cortex-R4 CPU @500 MHz
    • Up to 2 Mbytes of SRAM
    • Up to 4 Mbytes of stacked Flash or 16 Mbyte external Flash with update via communication interfaces
    Block Diagram -- Image Signal Processor (5MP, 2X Sensors) IP
  • Unified Deep Learning Processor
    • Unified deep learning/vision/video architecture enables flexibility
    • Low power extends battery life and prevents overheating
    • Single scalable architecture
  • Scalable and flexible display processor
    • Leading Performance per Area
    • Extreme Low Power Design
    • Display Output
    • AXI bus Interfaces
  • Configurable UART with FIFO, software and hardware flow control
    • Software compatible with 16450, 16550,16650,16750 and 16950 UARTs
    • Configuration capability
    • Separate configurable BAUD clock line
    • Majority Voting Logic
    Block Diagram -- Configurable UART with FIFO, software and hardware flow control
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Semiconductor IP