64-bit RISC-V Application Processor Core

Overview

The A70 is a powerful 64-bit RISC-V application processor aimed at systems running Linux. The core has an in-order 7-stage pipeline enabling greater than 1 GHz frequencies in 22nm HPC.
The core includes integrated L1 data and instruction caches, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like all Codasip RISC-V cores it is possible to create custom instructions using Codasip Studio to extend the ISA and to generate corresponding hardware and software development kits.
Tensor Flow Lite Micro is supported

Key Features

64-bit RISC-V core

RV64GC (GC=IMAFDC)

Linux capable
In-order 7-stage pipeline
RISC-V mode support:

Machine
Supervisor
User

Internal interrupt controller

Up to 256 sources

Dynamic jump prediction
Optional FPU
Integrated L1 data and instruction caches
MMU
On-chip debugger

JTAG and RISC-V Debug module

>1GHz clock in 22 nm

Benefits

Performance

High computational throughput with 7-stage pipeline and branch predictor
Support for RISC-V single and double precision FPU
Linux-ready with instruction cache, data cache and MMU

Extensibility

Ability to create custom RISC-V extensions to optimise performance
Efficient architectural exploration of custom extensions with Studio
Automatic HDK and SDK generation from Studio
Rigorous verification of modified core using UVM

Block Diagram

Applications

Routers,
switches,
consumer electronics,
industrial

Deliverables

Human-readable and structured RTL in either:

Verilog
VHDL
System Verilog

Hardware development kit (HDK)

Synthesis scripts
Simulation testbenches
Debug support

Software development kit (SDK)

GCC C-compiler
Assembler
Disassembler
Linker
Instruction-accurate simulator
Cycle-accurate simulator
Profiler

Options for extending A70

CodAL model for Codasip Studio
Full-feature Studio tool for extending A70X core
GUI for rapid development and debugging
Automatic HDK & SDK generation

Technical Specifications

Foundry, Node

Any

Availability

now

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