Vendor: Zipcores Electronic Systems Engineering S.L. Category: Display Controller

Graphics Processor Overlay IP Core

The GPU_OVERLAY IP Core is a versatile on-screen display processor that allows high-quality anti-aliased bitmap graphics and text…

Overview

The GPU_OVERLAY IP Core is a highly versatile on-screen display processor that allows high-quality anti-aliased bitmap graphics and text to be inserted over RGB video. The module supports a wide range of graphics effects and the programming interface is very simple to use. The bitmap overlay is partitioned into an array of tiles which are stored in a local tile buffer memory. There are four tile sizes available which are either: 8x16, 16x32, 32x64 or 64x128.

The tiles in the buffer are displayed in a graphics window which may be positioned anywhere within the display area. Bitmaps for each tile are defined in a ROM which can contain up to 128 different bitmaps stored over three bit-planes. Depending on the chosen graphics mode, the 3- bits per pixel may be used to select one colour from a palette of eight, eight levels of alpha transparency or seven colours on a transparent background. There is also a feature to highlight a tile with a background colour. This is especially useful for interactive text-based menus and lists where the user has to select an option.

Pixels flow in and out of the overlay module in accordance with a simple streaming (valid/ready) protocol. Pixels and syncs are sampled at the module inputs on a rising clock-edge when pixin_val is high and pixin_rdy is high. Likewise, pixels and syncs are transferred out of the module on a rising clock-edge when pixout_val and pixout_rdy are asserted high. The streaming protocol allows both input and output interfaces to be stalled independently.

The streaming protocol is very versatile and permits any number of GPU overlay modules to be cascaded in series. By placing more than one module together, the user is able to achieve more complex text and graphics displays with different fonts and colours.

Key features

  • Technology independent soft IP Core for FPGA, ASIC and SoC devices
  • Supplied as human-readable VHDL (or Verilog) source code
  • Fully pipelined architecture with input/output flow-control and AXI4-compatible data streaming interfaces
  • Supports both text and graphics (bitmap) overlays over realtime video
  • Support for RGB pixels in/out (YCbCr formats on request)
  • Support for all video resolutions up to 4096x4096 pixels
  • No external memory or frame buffer required
  • Bitmaps organized into tiles with a choice of four possible tile sizes: 8x16, 16x32, 32x64 or 64x128
  • Tiles organized into 3 bit-planes offering 3-bits/pixel
  • Programmable text and graphics map directly to the display
  • Programmable graphics-window position and size - offers functionality like a 2D ‘blitter’ but without the need for an external memory
  • Programmable window clipping region
  • Independent horizontal and vertical scrolling
  • Choice of 8 x 24-bit colours from a user defined palette or per-pixel alpha blending with 8 levels of transparency
  • Per-pixel alpha-blending removes jagged edges to give a smooth anti-aliased result
  • User-defined 8-bit alpha transparency
  • No complex programming required
  • Cascade any number of cores in series for more complex text and graphical displays
  • Optional I2C, SPI or UART interfaces for simple programming

Block Diagram

Applications

  • Clear and functional video overlays (on screen displays) featuring text and graphics
  • Digital TV and home-media solutions
  • Interactive guides, menus, tables, lists
  • Animated graphics including hardware ‘sprites’, pointers, cursors, scrolling text, moving banners
  • Instrumentation and monitoring applications including animated gauges, charts, dials, meters, counters
  • Informational displays and simple HUDs for commercial, military and automotive applications

Files

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
GPU_OVERLAY
Vendor
Zipcores Electronic Systems Engineering S.L.
Type
Silicon IP

Provider

Zipcores Electronic Systems Engineering S.L.
HQ: Spain
Zipcores design and sell IP Cores for implementation on all semiconductor devices. Founded in 2008, we are a team of experienced Engineers with a broad knowledge of digital hardware design spanning various fields. Our specific areas of expertise include Digital Video, DSP, Digital Modulation and high-speed interfaces. We offer a wide range of IP Cores for a variety of applications from basic building blocks to more complex systems. Our cores are supplied as clear readable VHDL or Verilog source-code and are synthesizable across multiple technologies - whether it be FPGA, ASIC or SoC.

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Frequently asked questions about Display Controller IP

What is Graphics Processor Overlay IP Core?

Graphics Processor Overlay IP Core is a Display Controller IP core from Zipcores Electronic Systems Engineering S.L. listed on Semi IP Hub.

How should engineers evaluate this Display Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Display Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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